公开(公告)号：EP2228727A2

公开(公告)日：2010-09-15

申请号：EP10167240.0

申请日：2004-07-12

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John ,  Massalin, Alexia

IPC: G06F12/00

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.

公开(公告)号：EP1879103A2

公开(公告)日：2008-01-16

申请号：EP07112545.4

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A wireless device for processing streams of media data in a wireless bi-directional communications network. The bi-directional communications network is capable of transmitting and receiving media data streams which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The wireless device has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.

Abstract translation: 一种用于在无线双向通信网络中处理媒体数据流的无线设备。 双向通信网络能够发送和接收包括音频，视频，无线电，图形，加密，认证和网络信息中的至少两个的组合的媒体数据流。 无线设备具有至少一个可编程媒体处理器（12），用于通过双向通信网络接收，处理和发送媒体数据流。 处理器执行组指令以从寄存器文件（110）读取媒体数据流的多个数据元素，以对数据元素执行包括能够动态划分数据的组整数和组浮点运算的组操作 通过每个指定多个数据元素大小中的一个，并将连接的结果写入寄存器文件。

公开(公告)号：EP1879398B1

公开(公告)日：2012-06-06

申请号：EP07112548.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1873630B8

公开(公告)日：2012-02-29

申请号：EP07111352.6

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP2228727A3

公开(公告)日：2010-10-20

申请号：EP10167240.0

申请日：2004-07-12

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John ,  Massalin, Alexia

IPC: G06F12/00 ,  H03M13/41

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.

公开(公告)号：EP2226725A2

公开(公告)日：2010-09-08

申请号：EP10167233.5

申请日：2004-07-12

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Massalin, Alexia ,  Moussouris, John

IPC: G06F12/00

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.

Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且通过使用通用寄存器的内容来显着地大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度可访问数量，则获得性能优点。

公开(公告)号：EP1879102A3

公开(公告)日：2009-02-25

申请号：EP07112538.9

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A system for processing streams of media data in a wireless bi-directional communications network. The system is capable of transmitting and receiving at least one stream of media data comprising a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information to and from system devices. The system devices each have at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.

公开(公告)号：EP1879103A3

公开(公告)日：2008-12-24

申请号：EP07112545.4

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A wireless device for processing streams of media data in a wireless bi-directional communications network. The bi-directional communications network is capable of transmitting and receiving media data streams which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The wireless device has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.

Abstract translation: 一种用于在无线双向通信网络中处理媒体数据流的无线设备。 双向通信网络能够发送和接收包括音频，视频，无线电，图形，加密，认证和联网信息中的至少两种的组合的媒体数据流。 无线设备具有至少一个可编程媒体处理器（12），用于通过双向通信网络接收，处理和发送媒体数据流。 处理器执行组指令以从寄存器文件（110）读取媒体数据流的多个数据元素，以对数据元素执行包括能够动态分区数据的组整数和组浮点操作的组操作 每个指定多个数据元素大小中的一个，并将连接结果写入寄存器文件。

公开(公告)号：EP1873630A2

公开(公告)日：2008-01-02

申请号：EP07111352.6

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1879103B1

公开(公告)日：2012-03-07

申请号：EP07112545.4

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.