公开(公告)号：JP2009176994A

公开(公告)日：2009-08-06

申请号：JP2008014796

申请日：2008-01-25

Applicant: Nec Corp ,  日本電気株式会社

Inventor： NAKASE KOICHIRO ,  KAWAHARA HIDENORI

IPC: H05K3/46 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To make a substrate or a module compact.
SOLUTION: A semiconductor incorporated substrate comprises: a semiconductor component having a through electrode; and a substrate having electrodes provided on a top surface and backside of the semiconductor component and connected to the through electrode. Alternatively, a semiconductor integrated substrate comprises: semiconductor components having through electrodes and stacked in layers to have at least portions of the through electrodes electrically connected to each other; and a substrate having electrodes provided on the top surface of the top stage and the backside of the bottom stage of the semiconductor components stacked in the layers and connected to the through electrodes.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：使基板或模块紧凑。 解决方案：半导体结合基板包括：具有通孔的半导体部件; 以及具有设置在半导体部件的顶表面和背面并连接到通孔的电极的基板。 或者，半导体集成基板包括：半导体部件，其具有通过电极并堆叠成层以使至少部分通孔彼此电连接; 以及基板，其具有设置在堆叠在层中并连接到通孔的半导体部件的顶部的顶表面和底部的底侧的电极。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007317848A

公开(公告)日：2007-12-06

申请号：JP2006145365

申请日：2006-05-25

Applicant: Nec Corp ,  日本電気株式会社

Inventor： NAKASE KOICHIRO

IPC: H05K3/34

CPC classification number: Y02P70/613

Abstract: PROBLEM TO BE SOLVED: To provide a component mounting board which is capable of reducing the number of mounting lands of 0 Ω resistance without revising a printed wiring board and enabling the miniaturization of an apparatus. SOLUTION: The mounting lands for a chip component are generally rectangular, so that the mounting direction of the chip component is limited to a certain direction. When the mounting lands 601a to 601d are set square, and a space between the adjacent mounting lands is set constant; two 0 Ω chip-resistances can be arranged in parallel in both a longitudinal direction and a lateral direction. Furthermore, a circuit switches connection between a pair of signal terminals, a terminal 602a and a terminal 602d, and between the other pair of signal terminals, and a terminal 602b and a terminal 602c. The switching circuit is composed of a first circuit formed of the terminals 602a, the land 601a, and wiring 603a connecting them; a second circuit formed of the terminals 602b, the land 601b, and wiring 603b connecting them; a third circuit formed of the terminals 602d, the land 601d, and wiring 603d connecting them; and a fourth circuit formed the terminals 602c, the land 601c, and wiring 603c connecting them. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够减少0Ω电阻的安装焊盘数量而不修改印刷电路板并使装置小型化的部件安装板。 解决方案：用于芯片部件的安装平台通常是矩形的，使得芯片部件的安装方向被限制在一定方向。 当安装台面601a至601d被设置成正方形，并且相邻安装台面之间的空间被设定为恒定时; 两个0Ω芯片电阻可以在纵向方向和横向方向上平行布置。 此外，电路切换一对信号端子，端子602a和端子602d之间以及另一对信号端子之间的连接以及端子602b和端子602c。 开关电路由端子602a，接地区601a和连接它们的布线603a构成的第一电路构成; 由端子602b，焊盘601b和连接它们的布线603b形成的第二电路; 由端子602d，焊盘601d和连接它们的连线603d形成的第三电路; 以及形成端子602c，焊盘601c以及连接它们的布线603c的第四电路。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002260959A

公开(公告)日：2002-09-13

申请号：JP2001056950

申请日：2001-03-01

Applicant: NEC CORP

Inventor： MORI TORU ,  YAMAZAKI TAKAO ,  NAKASE KOICHIRO

IPC: H01G4/12 ,  H01G4/30 ,  H01G4/38 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/40

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer capacitor having a high capacitance per unit mounting area as a decoupling capacitor being disposed on the periphery of an LSI operating at high speed and compensating for voltage drop when the load on the LSI is varied. SOLUTION: In the multilayer capacitor where dielectric and inner electrode are laid alternately in layers in order to reduce self inductance, a plurality of terminal electrodes for external connection are provided, respectively, on two bottom faces while being arranged two-dimensionally. The inner electrode is provided alternately with a layer connected electrically with the power supply of the LSI and a layer being connected electrically with the ground of the LSI and arranged with terminal electrodes connected, through via electrodes, with the inner electrodes connected electrically with the power supply of the LSI and terminal electrodes connected, through via electrodes, with the inner electrodes connected electrically with the ground of the LSI.