公开(公告)号：JPS59128646A

公开(公告)日：1984-07-24

申请号：JP309783

申请日：1983-01-12

Applicant: Nec Corp

Inventor： TENMA TSUTOMU

IPC: G06F15/82 ,  G06F9/44

CPC classification number: G06F9/44

Abstract: PURPOSE:To reduce the size of an input data storing circuit necessary for a processing module and a data storing circuit for data driving or to rekove these circuits by regulating the data transfer time intervals of the same variable. CONSTITUTION:Data are inputted to a data memory part 10 and an input status signal is sent to an output interval controlling part 20. Data indicating time are applied from a timer part 30 to the control part 20. The control part 20 forms an address in accordance with the variable name of the data, outputs the address information and monitors the output time interval in every variable name. If an output condition is satisfied, the control part 20 outputs a signal indicating the existence of the variable name and output data and the address of the input data. Consequently, the data read out from the memory 10 are outputted to a data line 51 together with the variable name. Thus, the size of the input data storing circuit or the like can be reduced or removed by regulating the data transfer time interval.

Abstract translation: 目的：减小处理模块所需的输入数据存储电路的大小和用于数据驱动的数据存储电路，或通过调节同一变量的数据传送时间间隔来重新取出这些电路。 构成：将数据输入到数据存储部10，将输入状态信号发送到输出间隔控制部20.从定时器部30向控制部20施加指示时间的数据。控制部20形成 根据数据的变量名称，输出地址信息并监视每个变量名称中的输出时间间隔。 如果满足输出条件，则控制部分20输出指示存在变量名称和输出数据的信号以及输入数据的地址。 因此，从存储器10读出的数据与变量名称一起被输出到数据线51。 因此，可以通过调节数据传送时间间隔来减少或去除输入数据存储电路等的大小。