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公开(公告)号：US20240048150A1
公开(公告)日：2024-02-08
申请号：US17880868
申请日：2022-08-04
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/354
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
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公开(公告)号：US20230017344A1
公开(公告)日：2023-01-19
申请号：US17809315
申请日：2022-06-28
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale
Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.
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公开(公告)号：US20210126648A1
公开(公告)日：2021-04-29
申请号：US17065731
申请日：2020-10-08
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.
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公开(公告)号：US10164807B2
公开(公告)日：2018-12-25
申请号：US15481038
申请日：2017-04-06
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems
Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analog-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analog-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
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公开(公告)号：US20170149388A1
公开(公告)日：2017-05-25
申请号：US15342009
申请日：2016-11-02
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Breems , Johannes Brekelmans , Jan Niehof
CPC classification number: H03D7/12 , H03F1/3211 , H03F3/45183 , H03F3/45475 , H03F2200/331 , H03F2203/45138 , H03M3/422 , H03M3/454 , H03M3/476
Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11502699B1
公开(公告)日：2022-11-15
申请号：US17357467
申请日：2021-06-24
Applicant: NXP B.V.
Inventor： Robert Rutten , Hendrik van der Ploeg , Lucien Johannes Breems , Martin Kessel , Muhammed Bolatkale , Bernard Burdiek , Manfred Zupke , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
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公开(公告)号：US20220091239A1
公开(公告)日：2022-03-24
申请号：US17030733
申请日：2020-09-24
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Dongjin Son , Maxim Kulesh
IPC: G01S7/4863 , G04F10/00 , G01S17/18
Abstract: Exemplary aspects of the present disclosure involve a SPAD receiver having circuitry for photon detection and having a plurality TDCs (time-to-digital converters) to detect multiple photons. Such circuitry may be set to accumulate photon counts over relatively coarse time ranges. In such accumulation of photons in relatively coarse time ranges, photon counts may be binned for each time range. Possible targets may then be identified by examination of the bins. Upon identification of the possible targets, a plurality of TDCs may be used over a more refined time ranges such as the time ranges corresponding to the identified possible target or targets.
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公开(公告)号：US11271585B2
公开(公告)日：2022-03-08
申请号：US17065731
申请日：2020-10-08
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.
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公开(公告)号：US11038522B1
公开(公告)日：2021-06-15
申请号：US16779976
申请日：2020-02-03
Applicant: NXP B.V.
Inventor： Johan Frederik Witte , Lucien Johannes Breems , Robert Rutten , Muhammed Bolatkale , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria , Albertus Willibrordus Oude Essink
Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.
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公开(公告)号：US10439634B2
公开(公告)日：2019-10-08
申请号：US15935045
申请日：2018-03-25
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems
Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.
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