公开(公告)号：EP3111179B1

公开(公告)日：2020-07-22

申请号：EP15710030.6

申请日：2015-02-20

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  KENNEDY, Adam M. ,  BLACK, Stephen H. ,  KOCIAN, Thomas Allan ,  DIEP, Buu

IPC: G01J5/04 ,  G02B19/00 ,  H01L23/26

公开(公告)号：EP3525233A1

公开(公告)日：2019-08-14

申请号：EP19163821.2

申请日：2013-06-18

Applicant: Raytheon Company

Inventor： DIEP, Buu ,  BLACK, Stephen H.

IPC: H01L21/56 ,  G01J5/02

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

公开(公告)号：EP2915190B1

公开(公告)日：2018-03-07

申请号：EP13850327.1

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.