DETECTOR GENERATING A DISPLACEMENT SIGNAL BY INJECTION LOCKING AND INJECTION PULLING
    11.
    发明公开
    DETECTOR GENERATING A DISPLACEMENT SIGNAL BY INJECTION LOCKING AND INJECTION PULLING 审中-公开
    探测器用于产生信号偏移通过注射和注射PULL LOCK

    公开(公告)号:EP3089358A3

    公开(公告)日:2017-03-08

    申请号:EP16164238.4

    申请日:2016-04-07

    Inventor: Chen, Tse-Peng

    Abstract: A detector (200) includes an oscillation source (210), a frequency multiplier (220), a transceiver (230) and a demodulator (240). The oscillation source (210) generates a first injection signal (Vi1) with a first frequency (f1). The frequency multiplier (220) receives the first injection signal (Vi1), outputs an output signal (Vo) and receives a second injection signal (Vi2) with a second frequency (f2). The frequency multiplier (220) uses injection locking to lock a frequency of the output signal (Vo) at a multiple of the first frequency (f1), and uses injection pulling to pull the frequency of the output signal (Vo) to the second frequency (f2). The transceiver (230) transmits the output signal (Vo) and receives a received signal (Vrx) with a third frequency (f3) for updating the second injection signal (Vi2). The demodulator (240) performs a demodulation operation according to the output signal (Vo) so as to generate a displacement signal (Vd).

    Abstract translation: 检测器(200)包括在振荡源(210),一个倍频器(220),收发机(230)和解调器(240)。 振荡源(210)基因速率的第一注入信号(Vi1的)以第一频率(F1)。 倍频器(220)接收第一注入信号(Vi1的),输出信号的输出(VO),并接收具有第二频率(F2)的第二注入信号(Vi2的)。 倍频器(220)使用注入锁定在所述第一频率(F1)的倍数来锁定的输出信号(VO)的频率,并使用注入牵引到所述输出信号(VO)的频率拉到第二频率 (F2)。 该收发器(230)发送的输出信号(VO),并接收与一个第三频率(F3),用于更新第二喷射信号(Vi2的)的接收信号(VRX)。 解调器(240)执行解调操作gemäß到输出信号(VO),从而生成的位移信号(VD)。

    DETECTOR GENERATING A DISPLACEMENT SIGNAL BY INJECTION LOCKING AND INJECTION PULLING
    12.
    发明公开
    DETECTOR GENERATING A DISPLACEMENT SIGNAL BY INJECTION LOCKING AND INJECTION PULLING 审中-公开
    探测器用于产生信号偏移通过注射和注射PULL LOCK

    公开(公告)号:EP3089358A2

    公开(公告)日:2016-11-02

    申请号:EP16164238.4

    申请日:2016-04-07

    Inventor: Chen, Tse-Peng

    Abstract: A detector (200) includes an oscillation source (210), a frequency multiplier (220), a transceiver (230) and a demodulator (240). The oscillation source (210) generates a first injection signal (Vi1) with a first frequency (f1). The frequency multiplier (220) receives the first injection signal (Vi1), outputs an output signal (Vo) and receives a second injection signal (Vi2) with a second frequency (f2). The frequency multiplier (220) uses injection locking to lock a frequency of the output signal (Vo) at a multiple of the first frequency (f1), and uses injection pulling to pull the frequency of the output signal (Vo) to the second frequency (f2). The transceiver (230) transmits the output signal (Vo) and receives a received signal (Vrx) with a third frequency (f3) for updating the second injection signal (Vi2). The demodulator (240) performs a demodulation operation according to the output signal (Vo) so as to generate a displacement signal (Vd).

    Digital phase-locked loops and frequency adjusting methods thereof
    13.
    发明授权
    Digital phase-locked loops and frequency adjusting methods thereof 有权
    数字锁相环和频率控制方法

    公开(公告)号:EP2302800B1

    公开(公告)日:2013-11-20

    申请号:EP10003775.3

    申请日:2010-04-08

    Inventor: Chen, Tse-Peng

    CPC classification number: H03L7/085 H03L7/0891 H03L7/18 H03L2207/50

    Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and -I. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

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