-
公开(公告)号：JP2014082768A
公开(公告)日：2014-05-08
申请号：JP2013244927
申请日：2013-11-27
Inventor： ISHIDA MINORU
Abstract: PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of easily photographing user's preferred images.SOLUTION: The imaging apparatus includes: an imaging unit group having plural imaging units disposed being aligned in a shorter edge of a housing on one plane of the housing; and a control section that controls an image range. The image range is any of an image range in which a part of the imaging units is used and an image range as a display target, a recording target or a transmission target. The control section selects and sets one of plural ranges (plural ranges in which the ratio of a longer edge with respect to a shorter edge of a generally rectangular shape is different from each other) as the image range.
Abstract translation: 要解决的问题：提供一种能够容易地拍摄用户喜好的图像的成像装置。解决方案：成像装置包括：具有多个成像单元的成像单元组，其设置成在壳体的一个平面上的壳体的较短边缘中对准; 以及控制图像范围的控制部。 图像范围是使用一部分成像单元的图像范围和作为显示目标的图像范围，记录目标或发送目标的图像范围中的任一个。 控制部选择并设定多个范围（长边相对于大致矩形的短边的比例彼此不同的多个范围）中的一个作为图像范围。
-
公开(公告)号：JP2013016846A
公开(公告)日：2013-01-24
申请号：JP2012202822
申请日：2012-09-14
Inventor： ISHIDA MINORU
IPC: H01L21/8244 , H01L27/11
CPC classification number: H01L2224/4813 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To effectively prevent deterioration in characteristics due to patter deviation at the time of forming a gate while inhibiting an increase in cell area, and achieve low resistance of a power source voltage supply line.SOLUTION: A semiconductor storage device comprises memory cells each including two inverters each having an input and an output being connected with an output and an input of another inverter in a crossing manner. The inverters include first conductivity type driving transistors Qn1, Qn2 and second conductivity type load transistors Qp1, Qp2, respectively, which are electrically connected in series between a first power source voltage supply line VCC and a second power source voltage supply line VSS with gates being connected in common with each other. At least one of the first power source voltage supply line VCC and the second power source voltage supply line VSS is composed of a groove wiring formed by burying a conductive material in a penetration groove in an interlayer insulation layer.
Abstract translation: 要解决的问题：为了有效地防止在形成栅极时由于图案偏离而导致的特性劣化，同时抑制电池面积的增加，并且实现电源电压供应线的低电阻。 解决方案：半导体存储装置包括存储单元，每个存储单元包括两个反相器，每个反相器具有输入和输出，以交叉的方式与另一个反相器的输出和输入连接。 反相器包括分别电连接在第一电源电压线VCC和第二电源电压线VSS之间的第一导电型驱动晶体管Qn1，Qn2和第二导电类型负载晶体管Qp1，Qp2，栅极为 彼此相通。 第一电源电压线VCC和第二电源电压线VSS中的至少一个由在层间绝缘层的贯通槽中埋入导电材料而形成的沟槽布线构成。 版权所有（C）2013，JPO＆INPIT
-
公开(公告)号：JP2004355676A
公开(公告)日：2004-12-16
申请号：JP2003149592
申请日：2003-05-27
Inventor： ISHIDA MINORU , ARAYA KATSUHISA , KOCHIYAMA AKIRA
CPC classification number: G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C16/3459 , G11C2013/009
Abstract: PROBLEM TO BE SOLVED: To provide a storage device by which a recording operation is well attained without any restriction even if information recording is continuously performed. SOLUTION: The storage device has a memory element and an applying means for applying a voltage to the memory element wherein the memory element changes its characteristic to record thereon information with application of a voltage to the memory element by the applying means, the memory element further changing its characteristic when the same information is recorded on the memory element continuously. When the information is recorded, the content of the information already recorded on the memory element is detected, and the information that already recorded on the memory element is compared with the information to be recorded on the memory element. A voltage is applied to the memory element to make an ordinary information recording process if the two information are different from each other, and the ordinary information recording process is disabled when the two information are identical to each other. COPYRIGHT: (C)2005,JPO&NCIPI
-
公开(公告)号：JP2001035938A
公开(公告)日：2001-02-09
申请号：JP2000065727
申请日：2000-03-06
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L21/768 , H01L21/8244 , H01L27/02 , H01L27/11
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device for simplifying a manufacturing process by easily forming a landing pad layer for a contact linked with a power source line and a bit line in the same hierarchy as that of node wiring, and a method for manufacturing the semiconductor storage device. SOLUTION: Almost C-shaped resist patterns R61a and (R61b) (that is, two node writing patterns) are formed so that the directions can not be made the same in all memory cells but made mutually different among upper and lower and right and left adjacent cells. Also, resist patterns R63a and (R63b) (that is, landing pad layer patterns) are formed on two sides other than two sides adjacent to the resist patterns R61a and (R61b) among the four sides of each memory cell. Thus, it is possible to form a landing pad layer in the same hierarchy as that of node wiring for a contact linked with a ground line, a power source line, and a bit line in the upper layer of that of node wiring 61a and 61b.
-
公开(公告)号：JP2000223591A
公开(公告)日：2000-08-11
申请号：JP1898199
申请日：1999-01-27
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L27/11 , G11C11/412 , H01L21/8244
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can reduce the size of a memory cell and realize high integration. SOLUTION: A drive transistor Qn1 and a word transistor Qn3 are formed on a p-type active region 11a. Similarly, a drive transistor Qn2 and a word transistor Qn4 are formed on a p-type active region 11b. A word line(WL) 14 is arranged nearly perpendicular to both of the two p-type active regions 11a and 11b. A pMOS load transistor Qp1 is formed on an n-type active region 12a, and a load transistor Qp2 is formed on an n-type active region 12b. A length DTw of the drive transistor is longer than a length LTw of the load transistor. Thereby a cell area can be made smaller than that of prior art SRAM cell, while obtaining the same cell current and the same SNM.
-
Patent Agency Ranking
公开(公告)号：JP2000174141A
公开(公告)日：2000-06-23
申请号：JP34170598
申请日：1998-12-01
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L27/11 , H01L21/8244
Abstract: PROBLEM TO BE SOLVED: To enable a semiconductor storage device in which first and second transistor forming areas are arranged in such a way that the areas are extended in the same direction as that of bit lines to operate at a high speed by reducing the resistance values of a power supply potential supplying line and a reference potential supplying line so that a sufficient potential may by supplied into cells. SOLUTION: In a layer which is different from the layer in which a VDD line 2a and a VSS line 2b are formed, an auxiliary VDD line 5a and an auxiliary VSS line 5b are provided in the direction perpendicular to the extended direction of the VDD and VSS lines 2a and 2b. The VDD and VSS lines 2a and 2b are electrically connected to the VDD line 2a and VSS line 2b in a third layer through contact sections 6a and 6b provided in each memory cell. Therefore, a sufficient potential can be supplied into each memory cell, because the resistance values of the VDD and VSS lines 2a and 2b are reduced and the occurrence of potential rises and potential drops caused by wiring resistances is reduced.
-
公开(公告)号：JPH0671299B2
公开(公告)日：1994-09-07
申请号：JP29833985
申请日：1985-12-30
Applicant: SONY CORP
Inventor： KUSAKA SATORU , ISHIDA MINORU , WATANABE HIDEO
-
公开(公告)号：JPH06244369A
公开(公告)日：1994-09-02
申请号：JP5513893
申请日：1993-02-19
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L21/28 , H01L21/8238 , H01L27/092
Abstract: PURPOSE:To suppress a decrease in a surface concentration of a gate electrode of a CMOS transistor, and to increase the speed of operation by preventing mutual diffusion through a silicide layer. CONSTITUTION:A CMOS transistor 1 is made up of a p-channel MOS transistor 2 having a p-type gate electrode 15, and an n-channel MOS transistor 3 having an n-type gate electrode 16. The p-type gate electrode 15 and the n-type gate electrode 16 are made of the same polusilicon layer 14, and a silicide layer 20 is formed on the polysilicon layer 14 with a diffusion prevention film 19 sandwiched between them. The CMOS transistor 1 is covered with an insulation film, and a connection hole is formed in this insulation film in such a way that it passes through the silicide layer 20 and the diffusion prevention film 19 and reaches the polysilicon layer 14.
-
公开(公告)号：JPH06244131A
公开(公告)日：1994-09-02
申请号：JP5513993
申请日：1993-02-19
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L21/28 , H01L21/768 , H01L21/8244 , H01L23/522 , H01L27/11 , H01L21/90
Abstract: PURPOSE:To form a shared contact hole without damaging a substrate, after a contact hole is formed in a self-alignment manner, regarding a method of forming a contact hole which is suitable to high level integration. CONSTITUTION:Gate electrodes 23, 24 and 26 as first, second and third patterns are formed on a semiconductor substrate 11. Side wall insulating films 44, 45, 46, 47, 48 are formed on the side walls of the respective gate electrodes 23, 24, 26, and an insulating film 49 covering the films 44, 45, 46, 47, 48 is formed. A first contact hole 61 is formed between the gate electrodes 23 and 24, in a self-alignment manner, and a lead-out electrode 51 as an upper layer pattern is formed in the contact hole. A flattening film 52 which covers the lead-out electrode 51 is formed on the insulating film 49. A part of the flattening film 52, a part of the insulating film 49, and the side wall insulating film 48 are eliminated. Thereby a second contact hole 62 to serve as a shared contact hole is formed.
-
公开(公告)号：JPH06151847A
公开(公告)日：1994-05-31
申请号：JP31607692
申请日：1992-10-31
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L27/11 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L29/784
Abstract: PURPOSE:To provide a TFT and method of the manufacture thereof involving a smaller number of simple processes. CONSTITUTION:A film-shape TFT gate 3 is formed in a contact hole 2 formed in a substrate 1 and on the periphery of the hole. A TFT dielectric film 4 is also formed on the TFT gate on the periphery of the contact hole. A film- shape TFT channel 5 is formed in such a way that it is in contact with the TFT gate in the contact hole and positioned on the TFT dielectric film on the periphery of the hole.
-
-
-
-
-
-
-
-
-
Search Results
104
records
(took 0.032 seconds)
