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    SYSTEM AND METHODS FOR ENTROPY AND STATISTICAL QUALITY METRICS
    11.
    发明申请
    SYSTEM AND METHODS FOR ENTROPY AND STATISTICAL QUALITY METRICS 审中-公开
    ENTROPY和统计质量指标的系统和方法

    公开(公告)号：WO2018085676A1

    公开(公告)日：2018-05-11

    申请号：PCT/US2017/059961

    申请日：2017-11-03

    Applicant: STC.UNM

    Inventor： PLUSQUELLIC, James ,  CHE, Wenjie

    IPC: G06F21/44 ,  G06F21/70

    Abstract: The Distribution Effect is proposed for the HELP PUF that is based on purposely introducing biases in the mean and range parameters of path delay distributions to enhance entropy. The biased distributions are then used in the bitstring construction process to introduce differences in the bit values associated with path delays that would normally remain fixed. Offsets are computed to fine tune a token's digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings: a first population-based offset method computes median values using data from multiple tokens (i.e., the population) and a second chip-specific technique is proposed which fine tunes path delays using enrollment data from the authenticating token.

    Abstract translation: 分布效应被提出用于帮助PUF，其基于在路径延迟分布的均值和距离参数中故意引入偏差以增强熵。 然后在比特串构造过程中使用偏置分布来引入与通常保持固定的路径延迟关联的比特值的差异。 计算偏移以微调令牌的数字化路径延迟，作为使生成的比特串中的熵和可再现性最大化的手段：第一基于总体的偏移方法使用来自多个令牌（即，总体）的数据来计算中间值， 提出了一种特殊的技术，它使用来自认证令牌的注册数据来优化路径延迟。

    A PRIVACY-PRESERVING, MUTUAL PUF-BASED AUTHENTICATION PROTOCOL
    12.
    发明申请
    A PRIVACY-PRESERVING, MUTUAL PUF-BASED AUTHENTICATION PROTOCOL 审中-公开
    一个隐私保护，相互PUF为基础的认证协议

    公开(公告)号：WO2017123631A1

    公开(公告)日：2017-07-20

    申请号：PCT/US2017/013013

    申请日：2017-01-11

    Applicant: STC.UNM

    Inventor： PLUSQUELLIC, James ,  CHE, Wenjie ,  ISMARI, Dylan

    IPC: G06F21/30 ,  G06F21/70

    CPC classification number: G06F21/30 ,  G06F21/44 ,  G06F21/70 ,  H04L9/3278

    Abstract: An authentication protocol using a Hardware-Embedded Delay PUF ("HELP"), which derives randomness from within-die path delay variations that occur along the paths within a hardware implementation of a cryptographic primitive, for example, the Advanced Encryption Standard ("AES") algorithm or Secure Hash Algorithm 3 ("SHA-3"). The digitized timing values which represent the path delays are stored in a database on a secure server (verifier) as an alternative to storing PUF response bitstrings thereby enabling the development of an efficient authentication protocol that provides both privacy and mutual authentication.

    Abstract translation: 使用硬件嵌入延迟PUF（“HELP”）的认证协议，其从加密原语的硬件实现内的沿着路径发生的管芯内路径延迟变化导出随机性，用于 例如高级加密标准（“AES”）算法或安全散列算法3（“SHA-3”）。 表示路径延迟的数字化定时值被存储在安全服务器（验证器）上的数据库中，作为存储PUF响应位串的替代方案，从而使得能够开发提供隐私和相互认证的有效认证协议。

    RELIABILITY ENHANCEMENT METHODS FOR PHYSICALLY UNCLONABLE FUNCTION BITSTRING GENERATION
    14.
    发明申请
    RELIABILITY ENHANCEMENT METHODS FOR PHYSICALLY UNCLONABLE FUNCTION BITSTRING GENERATION 审中-公开
    用于物理不可靠函数的生成的可靠性增强方法

    公开(公告)号：WO2016100402A1

    公开(公告)日：2016-06-23

    申请号：PCT/US2015/065909

    申请日：2015-12-15

    Applicant: STC.UNM

    Inventor： PLUSQUELLIC, James

    IPC: G06F21/73 ,  G06F21/70

    CPC classification number: G06F21/73 ,  G06F17/18 ,  G06F21/604 ,  G06F21/70 ,  G06F21/71 ,  G09C1/00 ,  H04L9/3278

    Abstract: A Hardware-Embedded Delay Physical Unclonable Function ("HELP PUF") leverages entropy by monitoring path stability and measuring path delays from core logic macros. Reliability and security enhancing techniques for the HELP PUF reduce bit flip errors during regeneration of the bitstring across environmental variations and improve cryptographic strength along with the corresponding difficulty of carrying out model building attacks. A voltage-based enrollment process screens unstable paths on normally synthesized (glitchy) functional units and reduces bit flip errors by carrying out enrollment at multiple supply voltages controlled using on-chip voltage regulators.

    Abstract translation: 硬件嵌入式延迟物理不可克隆功能（“HELP PUF”）通过监控路径稳定性和测量核心逻辑宏的路径延迟来利用熵。 HELP PUF的可靠性和安全性增强技术减少了位串越过环境变化的再生期间的位翻转错误，并提高了加密强度以及进行模型构建攻击的相应难度。 基于电压的注册过程在正常合成（故障）功能单元上屏蔽不稳定的路径，并通过在使用片上稳压器控制的多个电源电压下进行注册来减少位翻转错误。

    SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
    15.
    发明申请
    SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS 审中-公开
    用于在电路中引导路径延迟变化的系统和方法，并生成容错位

    公开(公告)号：WO2015031683A1

    公开(公告)日：2015-03-05

    申请号：PCT/US2014/053276

    申请日：2014-08-28

    Applicant: STC.UNM

    Inventor： PLUSQUELLIC, James

    IPC: G06F11/30 ,  G06F11/16

    CPC classification number: H03K19/00323 ,  H03K3/84 ,  H03K19/00315 ,  H03K19/215 ,  H03K23/004 ,  H04L9/0662 ,  H04L9/0866

    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

    Abstract translation: 硬件嵌入延迟PUF（HELP）通过监视路径稳定性和测量核心逻辑宏的路径延迟来利用熵。 帮助包含处理偏见的技术。 HELP的一个独特之处在于可以比较不同测试结构测量的数据。 HELP可以在现有的FPGA平台上实现。 帮助可以利用路径稳定性和模内变化作为熵的来源。

    SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
    17.
    发明公开
    SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS 审中-公开
    系统和方法WEGVERZÖGERUNGSVARIATIONEN的电路中的开发与容错位串生产

    公开(公告)号：EP3039550A1

    公开(公告)日：2016-07-06

    申请号：EP14839346.5

    申请日：2014-08-28

    Applicant: STC.UNM

    Inventor： PLUSQUELLIC, James ,  AARESTAD, James

    IPC: G06F11/30 ,  G06F11/16

    CPC classification number: H03K19/00323 ,  H03K3/84 ,  H03K19/00315 ,  H03K19/215 ,  H03K23/004 ,  H04L9/0662 ,  H04L9/0866

    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

    Abstract translation: 硬件嵌入延迟PUF（HELP）通过监视路径的稳定性和测量从核心逻辑宏路径延迟利用熵。 HELP集成了技术处理偏差。 HELP的一个独特功能是没有可能从不同的测量测试结构的数据进行比较。 HELP可以在现有FPGA平台上实现。 HELP可以利用内-变化作为熵源两个路径和稳定性。

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