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公开(公告)号：US11641002B2
公开(公告)日：2023-05-02
申请号：US17199180
申请日：2021-03-11
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Alexandre Coullomb , Romain Coffy , Jean-Michel Riviere
Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
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公开(公告)号：US11437306B2
公开(公告)日：2022-09-06
申请号：US17165295
申请日：2021-02-02
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain Coffy , Fabien Quercia
IPC: H01L23/498 , H01L21/48 , H01L23/552 , H01L23/66 , H01L23/00 , H01Q1/22
Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
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公开(公告)号：US11211772B2
公开(公告)日：2021-12-28
申请号：US16432576
申请日：2019-06-05
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Romain Coffy , Jean-Michel Riviere
Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a barrel comprising a mounting for a diffuser; and a diffuser positioned in the mounting, wherein the barrel comprises first and second conducting columns and a fuse or conductive wire electrically coupling the first and second conducting columns. A portion of the fuse is mechanically fixed to the diffuser and/or the fuse being arranged to trap the diffuser in said mounting.
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公开(公告)号：US10978607B2
公开(公告)日：2021-04-13
申请号：US16409714
申请日：2019-05-10
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Alexandre Coullomb , Romain Coffy , Jean-Michel Riviere
Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
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公开(公告)号：US10965376B2
公开(公告)日：2021-03-30
申请号：US16218948
申请日：2018-12-13
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Jean-Michel Riviere , Romain Coffy , Karine Saxod
Abstract: A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.
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Patent Agency Ranking
公开(公告)号：US09401349B2
公开(公告)日：2016-07-26
申请号：US14723893
申请日：2015-05-28
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Malta) Ltd , STMicroelectronics S.r.l.
Inventor： Angelo Crobu , Kenneth Fonk , Romain Coffy
CPC classification number: H01L25/18 , G01L19/0084 , G01L19/147 , G01L19/148 , H01L23/24 , H01L23/3157 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/10135 , H01L2224/10165 , H01L2224/1319 , H01L2224/16145 , H01L2224/26122 , H01L2224/26135 , H01L2224/29007 , H01L2224/29021 , H01L2224/29036 , H01L2224/32014 , H01L2224/32111 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48106 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2224/83192 , H01L2224/83855 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2225/06575 , H01L2924/00014 , H01L2924/14 , H01L2924/146 , H01L2924/16151 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.
Abstract translation: 一堆芯片由第一集成电路芯片和第二集成电路芯片形成。 芯片具有通过插入的间隔件彼此分离的相对面。 间隔件通过粘合固定到只有一个相对的面。 相对的面通过与间隔物分离的局部粘合剂彼此紧固。
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公开(公告)号：US09105766B2
公开(公告)日：2015-08-11
申请号：US13845445
申请日：2013-03-18
Inventor： Romain Coffy , Eric Saugier , Hk Looi , Norbert Chevrier
IPC: H01L33/48 , H01L31/0203 , H01L31/18 , G01S17/02 , H01L25/16 , H03K17/94 , G01S7/481 , H03K17/945
CPC classification number: H01L31/0203 , G01S7/481 , G01S17/026 , H01L25/167 , H01L31/18 , H01L2224/48091 , H01L2224/49175 , H01L2924/181 , H03K17/941 , H03K2017/9455 , H03K2217/94026 , H03K2217/94112 , H01L2924/00014 , H01L2924/00012
Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.
Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。
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18.发明申请ELECTRONIC SYSTEM COMPRISING STACKED ELECTRONIC DEVICES COMPRISING INTEGRATED-CIRCUIT CHIPS 有权包含集成电路卡的堆叠式电子设备的电子系统公开(公告)号：US20150102500A1
公开(公告)日：2015-04-16
申请号：US14512060
申请日：2014-10-10
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain Coffy , Rémi Brechignac
IPC: H01L23/00 , H01L23/522
CPC classification number: H01L24/33 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5226 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/32146 , H01L2224/32225 , H01L2224/32235 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06575 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H05K1/144 , H01L2924/00012 , H01L2924/00
Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.
Abstract translation: 电子系统包括第一集成电路芯片和第二集成电路芯片。 第一衬底晶片位于第一和第二集成电路芯片之间并且配置有第一连接网络以与第一集成电路芯片进行电连接。 配置有与第二集成电路芯片进行电连接的第二连接网络的第二衬底晶片被定位成面向第一衬底晶片。 第一和第二衬底晶片的连接网络通过连接结构电连接。 包括第三连接网络的第三衬底晶片与第一集成电路芯片热接触，并通过另外的连接结构电连接到第一衬底晶片的第一连接网络。 另外的连接结构可以使用另一个衬底晶片形成。
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公开(公告)号：US09006904B2
公开(公告)日：2015-04-14
申请号：US13654850
申请日：2012-10-18
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Dominique Marais , Jacques Chavade , Rémi Brechignac , Eric Saugier , Romain Coffy , Luc Petit
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/367 , H01L25/065 , H05K1/02 , H05K3/34
CPC classification number: H01L25/0652 , H01L23/3677 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586 , H01L2225/06589 , H01L2924/00 , H01L2924/00012 , H01L2924/15311 , H01L2924/3011 , H05K1/0206 , H05K3/3436 , H05K2201/10515 , H05K2201/1053
Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
Abstract translation: 电子封装包括具有互连网络的衬底晶片。 第一芯片固定到基板的前部，连接到互连网络并由主体封装。 第二芯片放置在基板晶片的背面，并通过设置在基板的背面和第二芯片的前侧之间的背面连接元件连接到互连网络。 前端连接元件放置在基板的正面并连接到互连网络。 连接元件延伸超出身体的正面。 封装可以安装在具有插入的导热材料的板上。
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公开(公告)号：US11935992B2
公开(公告)日：2024-03-19
申请号：US17965443
申请日：2022-10-13
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain Coffy , Remi Brechignac , Jean-Michel Riviere
IPC: H01L33/52 , H01L31/0203 , H01L31/0216 , H01L33/44 , H01L33/62
CPC classification number: H01L33/52 , H01L31/0203 , H01L31/02164 , H01L33/44 , H01L33/62
Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
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