公开(公告)号：US20210273087A1

公开(公告)日：2021-09-02

申请号：US17322528

申请日：2021-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20180358458A1

公开(公告)日：2018-12-13

申请号：US16004272

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7378

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20240079455A1

公开(公告)日：2024-03-07

申请号：US18364180

申请日：2023-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/872

Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

公开(公告)号：US20230299148A1

公开(公告)日：2023-09-21

申请号：US18183866

申请日：2023-03-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Fabrizio ROCCAFORTE ,  Gabriele BELLOCCHI ,  Marilena VIVONA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/45

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/872 ,  H01L29/66143 ,  H01L29/45

Abstract: A method for manufacturing an electronic device includes forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

公开(公告)号：US20230246100A1

公开(公告)日：2023-08-03

申请号：US18158986

申请日：2023-01-24

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Filippo GIANNAZZO ,  Giuseppe Greco ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/285 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L29/7786 ,  H01L29/66431 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/0272 ,  H01L21/28506 ,  H01L21/3086 ,  H01L21/3081 ,  H01L21/3065 ,  H01L21/32051

Abstract: An enhancement mode high electron-mobility transistor (HEMT) device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG. The HEMT device includes a gate structure which extends on the top surface of the semiconductor body, is biasable to electrically control the 2DEG and includes a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity, which extends on the top surface of the semiconductor body and is interposed between the semiconductor body and the gate contact along a first axis.