公开(公告)号：EP1024668B1

公开(公告)日：2006-05-24

申请号：EP99309803.7

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/50

CPC classification number: H04N19/43 ,  H04N19/51

公开(公告)号：EP1009170A2

公开(公告)日：2000-06-14

申请号：EP99309802.9

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： McDade, Darryn ,  Owen, Jefferson Eugene

IPC: H04N7/36

CPC classification number: H04N19/43 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: The present invention provides a system, method and an apparatus for a digital video decoder, which includes a data processor that utilizes at least an encoded video data stream to produce one or more output streams. The one or more output streams includes at least a set of motion compensation instructions.

Abstract translation: 本发明提供了一种用于数字视频解码器的系统，方法和装置，其包括利用至少编码视频数据流来产生一个或多个输出流的数据处理器。 一个或多个输出流包括至少一组运动补偿指令。

公开(公告)号：EP1009169A2

公开(公告)日：2000-06-14

申请号：EP99309800.3

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/36 ,  H04N7/50

CPC classification number: H04N19/523

Abstract: The present invention provides a system, method and an apparatus for a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.

Abstract translation: 本发明提供了一种用于数字视频处理器的系统，方法和装置，包括错误存储器和合并存储器，可通信地耦合到合并存储器的半像素滤波器，可通信地耦合到错误存储器的控制器，合并存储器和 半像素滤光片 本发明还包括可通信地耦合到错误存储器的总和单元。 所述控制器执行一个或多个指令以在视频解码期间提供运动补偿。