公开(公告)号：US11848672B2

公开(公告)日：2023-12-19

申请号：US17719004

申请日：2022-04-12

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Jeena Mary George

IPC: H03K19/23 ,  G01R31/3185 ,  H03K19/20 ,  H03K19/00 ,  H03K3/037

CPC classification number: H03K19/23 ,  G01R31/318525 ,  G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20

Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.