公开(公告)号：EP4044431A1

公开(公告)日：2022-08-17

申请号：EP22153004.1

申请日：2022-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： MODAFFARI, Roberto ,  NICOLLINI, Germano

IPC: H03F3/45

Abstract: A circuit (50; 70) for startup of a multi-stage amplifier circuit (10) comprising a cascade of differential stages having at least a first differential stage (M 1 , M 2 ), the circuit (50; 70) comprising: a pair of input nodes (V SUp , V SUn ) and at least two output nodes (V 1p , V 1 ; V CP1 , V CP2 , V CN1 , V CN2 ) configured to be coupled to the multi-stage amplifier circuit (10), a startup differential stage comprising a differential pair of transistors (M SU1 , M SU2 ) having respective control terminals coupled to the pair of input nodes (V SUp , V SUn ), each transistor (M sui ) in the differential pair of transistors (M sui , M SU2 ) having a respective current path therethrough between a respective output node (V 1p , V 1n , V CP1 , V CP2 ) in the at least two output nodes (V 1p , V 1n ; V CP1 , V CP2 , V CN1 , V CN2 ), and a common source terminal, the startup differential stage configured to sense (M sui , M SU2 ) a common mode voltage drop at the first differential stage (M 1 , M 2 ) of the multi-stage amplifier circuit (10), current mirror circuitry (M SU3 , M SU4 , M SU5 ) comprising a plurality of transistors in a current mirror arrangement coupled to the common terminal of the first differential pair of transistors (M sui , M SU2 ) and having two output nodes in the at least two output nodes wherein at least two output nodes are configured to be coupled to the first differential stage (M 1 , M 2 ) of the multi-stage amplifier circuit (10)

公开(公告)号：EP3361636A1

公开(公告)日：2018-08-15

申请号：EP17187803.6

申请日：2017-08-24

Applicant: STMicroelectronics S.r.l.

Inventor： RAMORINI, Stefano ,  NICOLLINI, Germano ,  CATTANI, Alberto ,  GASPARINI, Alessandro

IPC: H03K4/06 ,  H03F3/217

Abstract: A triangular-voltage generator (20) for a class-D amplifier circuit (1) has an input terminal (IN) designed to receive a first power supply voltage (V HV ) and an output terminal (OUT) designed to supply a triangular-wave voltage (V TRI ) having a repetition period (T S ), and is provided with an operational amplifier (21) in integrator configuration, having a first input, a second input and an output coupled to the output terminal (OUT). The second input is designed to receive a reference voltage (V REF ), as a function of the first power supply voltage (V HV ), and the first input is designed to be selectively and alternately connected to the input terminal (IN) during a first half-period (T S /2) of the repetition period (T S ), via a first resistor element (R i1 ), and to a reference terminal (gnd) during a second half-period (T S/ 2) of the repetition period (T S ), via a second resistor element (R i2 ).

公开(公告)号：EP1751963B1

公开(公告)日：2009-05-13

申请号：EP05750127.2

申请日：2005-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74 ,  H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

公开(公告)号：EP1751963A1

公开(公告)日：2007-02-14

申请号：EP05750127.2

申请日：2005-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74 ,  H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

公开(公告)号：EP3828662A1

公开(公告)日：2021-06-02

申请号：EP20207694.9

申请日：2020-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： RAMORINI, Stefano ,  NICOLLINI, Germano

IPC: G05F3/30 ,  G05F3/26

Abstract: A bandgap circuit (10), for use in AMOLED display devices, for instance, comprises a supply node (V SUPPLY ) as well as a first bipolar transistor (Q 1 ) and a second bipolar transistor (Q 2 ), having their base terminals jointly coupled to a bandgap node to provide a bandgap voltage (V BG ) at the bandgap node. A first current generator (121a, 121b) and a second current generator (122a, 122b) coupled to the supply node (V SUPPLY ) are provide to supply a first current (I 1 ) and a second current (I 2 ) to a first circuit node (A) and a second circuit node (B), with the current (I 2 ) of the second current generator mirroring the current (I 1 ) of the first current generator. A third circuit node (D) is coupled to the current flow path through the first bipolar transistor (Q 1 ) via a first resistor (R 1 ) and coupled to ground (GND) via a second resistor (R 2 ), respectively. The third circuit node (D) is also coupled to the current flow path through the second bipolar transistor (Q 2 ) so that the second resistor (R 2 ) is traversed by a current which is the sum of the currents (I 1 , I 2 ) through the bipolar transistors (Q 1 and Q 2 ). Intermediate the current generators (121a, 121b; 122a, 122b) and the bipolar transistors (Q 1 , Q 2 ) a decoupling stage (200) is provided comprising a first (N 1 ) and a second (N 2 ) cascode decoupling transistor having their control terminals jointly coupled to a fourth circuit node (C) sensitive to the ground-referred bandgap voltage (V BG ).

公开(公告)号：EP3185416A1

公开(公告)日：2017-06-28

申请号：EP16175666.3

申请日：2016-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  GARBARINO, Marco

IPC: H03F3/70 ,  G01C19/5726 ,  H03F3/45

Abstract: An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier (2) with a feedback capacitor (C r1 ); a switch (RESET1) that drives charging and discharging of the feedback capacitor (C r1 ) ; an additional capacitor (C RES1 ) ; and a coupling circuit (RD1, RD2), which alternatively connects the additional capacitor (C RES1 ) in parallel to the feedback capacitor (C r1 ) or else decouples the additional capacitor (C RES1 ) from the feedback capacitor (C r1 ). The switch (RESET1) opens at a first instant (t 2 ), where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor (C RES1 ) from the feedback capacitor (C r1 ) in a way synchronous with a second instant (t 3 ), where the first component assumes a second zero value.

Abstract translation: 一种用于以相位正交的两个分量来放大信号的电子电路，其包括：具有反馈电容器（Cr1）的反馈放大器（2）; 驱动反馈电容器（Cr1）的充电和放电的开关（RESET1）; 一个额外的电容器（CRES1）; 和耦合电路（RD1，RD2），其交替地将附加电容器（CRES1）并联连接至反馈电容器（Cr1），或者将附加电容器（CRES1）与反馈电容器（Cr1）去耦合。 开关（RESET1）在第一时刻（t2）打开，其中两个分量中的第一个分量呈现第一零值; 耦合电路以与第二时刻（t3）同步的方式将附加电容器（CRES1）与反馈电容器（Cr1）分离，其中第一分量呈现第二零值。