Write driver with power optimization and interconnect impedance matching
    11.
    发明公开
    Write driver with power optimization and interconnect impedance matching 审中-公开
    写功率优化和互连阻抗匹配的驱动程序

    公开(公告)号:EP1587067A2

    公开(公告)日:2005-10-19

    申请号:EP05252273.7

    申请日:2005-04-12

    CPC classification number: G11B5/02

    Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

    Abstract translation: 用于驱动写入电流的写入驱动器通过由互连或柔性传输线连接到写入头的写入头。 写入驱动器包括将写入驱动器的输出阻抗匹配到互连的奇特性阻抗的电路,并且包括产生到写入头的电流输出的电流源。 写入驱动器提供电流放大效应,因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源,该电压源用于在互连的传输延迟的两倍的初始时段期间在输出电阻器上保持零电压降。

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