公开(公告)号：US20230309317A1

公开(公告)日：2023-09-28

申请号：US18059010

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol KIM ,  Yongseok Kim ,  Kiheun Lee ,  Sangkil Lee ,  Daewon Ha

IPC: H10B53/20 ,  H10B53/10 ,  H01L23/528

CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L23/5283

Abstract: A semiconductor memory device is provided. The semiconductor memory device may include a semiconductor substrate; a data storage layer including capacitors disposed on the semiconductor substrate; a switching element layer on the data storage layer and including transistors connected to the respective capacitors; and a wiring layer on the switching element layer and including bit lines connected to the transistors, The respective transistors include an active pattern, a word line that crosses the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern, and a ferroelectric layer between the word line and the active patter.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20190206867A1

公开(公告)日：2019-07-04

申请号：US16030224

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Han LEE ,  Sungchul Park ,  Yunil Lee ,  Byoung-gi Kim ,  Yeongmin Jeon ,  Daewon Ha ,  Inchan Hwang ,  Jae Hyun Park ,  Woocheol Shin

IPC: H01L27/092 ,  H01L29/423 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor substrate includes a plurality of gate electrodes crossing active patterns on a substrate and extending in a second direction, the gate electrodes spaced apart in the second direction from each other, a gate separation pattern having a major axis in the first direction and between two of the gate electrodes, the two of the gate electrodes adjacent to each other in the second direction, and a plurality of gate spacers covering sidewalls of respective ones of the gate electrodes, the gate spacers crossing the gate separation pattern and extending in the second direction. The gate separation pattern includes a lower portion extending in the first direction, an intermediate portion protruding from the lower portion and having a first width, and an upper portion between two adjacent gate spacers and protruding from the intermediate portion, the upper portion having a second width less than the first width.

公开(公告)号：US09208875B2

公开(公告)日：2015-12-08

申请号：US14162991

申请日：2014-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Woo Lee ,  Daewon Ha

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064

Abstract: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

Abstract translation: 提供了一种非易失性存储器件的写入方法，其接收数据，目标时间和目标电阻值; 将数据写入存储单元; 基于读取的存储器单元的电阻值计算电阻漂移系数至少两次; 使用电阻漂移系数计算目标时间上的存储单元的电阻值; 以及确定所计算的电阻值是否满足目标电阻值。

公开(公告)号：US12255206B2

公开(公告)日：2025-03-18

申请号：US17699724

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

公开(公告)号：US12166097B2

公开(公告)日：2024-12-10

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.

公开(公告)号：US11888044B2

公开(公告)日：2024-01-30

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/82

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US11832430B2

公开(公告)日：2023-11-28

申请号：US17363748

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu Kim ,  Munhyeon Kim ,  Daewon Ha

IPC: H10B10/00 ,  H01L29/10 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L29/1033

Abstract: A semiconductor device may include a pull-down transistor and a pull-up transistor disposed on a substrate. Each of the pull-down transistor and the pull-up transistor may include an active pattern disposed on the substrate; two source/drain patterns disposed on the active pattern; a channel pattern interposed between the two source/drain patterns, the channel pattern including semiconductor patterns that are disposed in a noncontiguous stack, such that a semiconductor pattern does not contact an adjacent semiconductor pattern; and a gate electrode crossing the channel pattern in a first direction. There may be more or less semiconductor patterns of the pull-down transistor as compared to semiconductor patterns of the pull-up transistor.

公开(公告)号：US20220285511A1

公开(公告)日：2022-09-08

申请号：US17455681

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.