公开(公告)号：US20240321726A1

公开(公告)日：2024-09-26

申请号：US18419715

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Yubo QIAN ,  Hyunjae KANG ,  Gyeongseop KIM ,  Sutae KIM ,  Jaeyoung PARK ,  Jeonwon JEONG

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L27/0886

Abstract: An integrated circuit device includes a first conductive pattern disposed on a substrate, a second conductive pattern surrounding a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulation structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern penetrating through the upper insulation structure and extending in a vertical direction, wherein the upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension extending from a portion of the main plug portion toward the substrate, covering an upper of the upper sidewall of the first conductive pattern, and overlapping the second conductive pattern in the vertical direction, and a dummy contact is formed on a single diffusion break region on the substrate.

公开(公告)号：US20240274598A1

公开(公告)日：2024-08-15

申请号：US18500636

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Hojun CHOI ,  Sutae KIM

IPC: H01L27/06 ,  H01L21/306 ,  H01L23/48 ,  H01L23/522 ,  H01L29/732

CPC classification number: H01L27/0623 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5226 ,  H01L29/7322

Abstract: The present disclosure relates to an integrated circuit element and a manufacturing method thereof. An integrated circuit element may include a substrate including a first region and a second region, a first element in the first region of the substrate and configured to generate an electric field in a horizontal direction, and a second element in the second region of the substrate and configured to generate an electric field is formed in a vertical direction, wherein a thickness of the second region of the substrate is thicker than a thickness of the first region.

公开(公告)号：US20240202879A1

公开(公告)日：2024-06-20

申请号：US18471504

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Bumjoo LEE ,  Su-Young LEE

IPC: G06T5/50 ,  G06T5/00 ,  G06T7/11 ,  G06T7/62

CPC classification number: G06T5/50 ,  G06T5/002 ,  G06T7/11 ,  G06T7/62 ,  G06T2207/20132 ,  G06T2207/20216

Abstract: An image processing method includes generating a full image of an area of interest in which unit patterns are repeatedly arranged, blurring each of the unit patterns, calculating respective center positions of each of the unit patterns based on the blurring, setting respective reference positions on each of the unit patterns based on the center positions, cropping the full image into a plurality of unit images, and merging the plurality of unit images based on the reference positions to generate an averaged image.

公开(公告)号：US20210254224A1

公开(公告)日：2021-08-19

申请号：US17313534

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungah KIM ,  Mihyun PARK ,  Jinwoo LEE ,  Keonyoung KIM ,  Hyosan LEE ,  Hoon HAN ,  Jin Uk LEE ,  Jung Hun LIM

IPC: C23F1/26 ,  C23F1/30 ,  H01L21/311 ,  H01L21/306

Abstract: A method of etching a metal barrier layer and a metal layer is provided. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.

公开(公告)号：US20200343113A1

公开(公告)日：2020-10-29

申请号：US16690498

申请日：2019-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jun CHOI ,  Seok Hoon KIM ,  Young-Hoo KIM ,  In Gi KIM ,  Sung Hyun PARK ,  Seung Min SHIN ,  Kun Tack LEE ,  Jinwoo LEE ,  Hun Jae JANG ,  Ji Hoon CHA

IPC: H01L21/67 ,  H01L21/687 ,  B08B3/08

Abstract: A multi-chamber apparatus for processing a wafer, the apparatus including a high etch rate chamber to receive the wafer and to etch silicon nitride with a phosphoric acid solution; a rinse chamber to receive the wafer and to clean the wafer with an ammonia mixed solution; and a supercritical drying chamber to dry the wafer with a supercritical fluid.

公开(公告)号：US20200087798A1

公开(公告)日：2020-03-19

申请号：US16574372

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SOULBRAIN CO., LTD.

Inventor： Jungah KIM ,  Mihyun PARK ,  Jinwoo LEE ,  Keonyoung KIM ,  Hyosan LEE ,  Hoon HAN ,  Jin Uk LEE ,  Jung Hun LIM

IPC: C23F1/26 ,  H01L21/306 ,  H01L21/311 ,  C23F1/30

Abstract: Disclosed is a method of etching a metal barrier layer and a metal layer. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.

公开(公告)号：US20240065001A1

公开(公告)日：2024-02-22

申请号：US18299403

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO,LTD.

Inventor： Seyun KIM ,  Jooheon KANG ,  Sunho KIM ,  Yumin KIM ,  Garam PARK ,  Hyunjae SONG ,  Dongho AHN ,  Seungyeul YANG ,  Myunghun WOO ,  Jinwoo LEE

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

公开(公告)号：US20230097159A1

公开(公告)日：2023-03-30

申请号：US17839724

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Chunyub PARK ,  Sutae KIM

IPC: H01L21/28 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on gate lines and intergate insulating portions alternately arranged; respectively forming mandrel lines on regions of the hardmask layer, corresponding to every other one of the intergate insulating portions; conformally forming a spacer material layer, having a thickness corresponding to a width of the gate lines, on the hardmask layer; forming a mandrel material layer on the spacer material layer; removing a portion of the mandrel material layer to expose portions of the spacer material layer on an upper surface and a side surface of the mandrel line; removing the exposed portions of the spacer material layer to provide the mandrel lines and stacked mandrel patterns; and forming an opening in the hardmask layer, which exposes a gate-cut region of the gate lines, using the mandrel lines and the stacked mandrel patterns as a mask.

公开(公告)号：US20150099470A1

公开(公告)日：2015-04-09

申请号：US14509160

申请日：2014-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Jiyeon SEO ,  Myunghwan LEE ,  Yongcheol CHA

IPC: H04W76/02 ,  H04W4/00

CPC classification number: H04W76/14 ,  H04W4/80 ,  H04W8/005

Abstract: Disclosed herein are a method and apparatus for pairing terminals using a sound wave. A sound wave is transmitted from a first terminal to a second terminal and a response is sent by the second terminal and detected by the first terminal. The first terminal and the second terminal are paired based at least partially on the sound wave signal and the response signal.

Abstract translation: 这里公开了一种使用声波配对终端的方法和装置。 声波从第一终端发送到第二终端，并且由第二终端发送响应并由第一终端检测。 至少部分地基于声波信号和响应信号来配对第一终端和第二终端。

公开(公告)号：US20250048723A1

公开(公告)日：2025-02-06

申请号：US18645844

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Sutae KIM

IPC: H01L27/088 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate having first and second surfaces; an active pattern extending on the first surface of the substrate, the active pattern having first and second conductivity-type impurity regions, the first and second conductivity-type impurity regions in contact with each other; semiconductor patterns stacked on a portion of the active pattern between the first and second conductivity-type impurity regions; an inactive gate structure extending across the portion of the active pattern between the first and second conductivity-type impurity regions, the inactive gate structure surrounding the semiconductor patterns; a first contact passing through the substrate from the second surface of the substrate and connected to the first conductivity-type impurity region; and a second contact passing through the substrate from the second surface of the substrate and connected to the second conductivity-type impurity region.