公开(公告)号：US20230401002A1

公开(公告)日：2023-12-14

申请号：US18132092

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Jinwook LEE ,  Dongouk MOON

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: A method of writing data in a storage device is provided. The method includes: receiving write data from a host device; monitoring an operating temperature of the storage device; generating a plurality of write data blocks respectively corresponding to a plurality of storage regions of the storage device based on the write data; and based on the operating temperature, performing a write throttling operation including performing a write operation on P write data blocks among the plurality of write data blocks by transmitting a write command to P storage regions among the plurality of storage regions and skipping the write operation on X write data blocks among the plurality of write data blocks by skipping an operation of transmitting the write command to X storage regions among the plurality of storage regions. P and X are natural numbers.

公开(公告)号：US20250169187A1

公开(公告)日：2025-05-22

申请号：US18753484

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Gunpil HWANG ,  Hyonwook RA ,  Keunhee BAI ,  Jinwook LEE ,  Sangho CHEON

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device may include a device isolation layer on a substrate and defining active regions extending a first direction; gate structures intersecting the active regions and extending in a second direction; channel layers spaced apart from each other on the active regions and surrounded by the gate structures; and source/drain regions connected to the channel layers and in recessed regions of the active regions on both sides of the gate structures. First and second regions of the substrate respectively may be spaced apart by a first length and the second length from first ends of the gate structures in the second direction. The second length may be longer than the first length. An upper surface of the device isolation layer may have recessed portion on the first region of the substrate and a flat upper surface on the second region of the substrate.

公开(公告)号：US20250107150A1

公开(公告)日：2025-03-27

申请号：US18650292

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesik KIM ,  Seonbae KIM ,  Taeyong KWON ,  Changhee KIM ,  Doohyun LEE ,  Jaehyun KANG ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jinwook LEE ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active region, a gate structure on the substrate, a plurality of channel layers on the active region, spaced apart from each other and surrounded by the gate structure, a source/drain region in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the channel layers, and a contact plug partially recessing the source/drain region from an upper surface of the source/drain region, electrically connected to the source/drain region, and including a metal-semiconductor compound layer along a recessed surface of the source/drain region and a contact conductor layer on the metal-semiconductor compound layer, wherein the metal-semiconductor compound layer has a first thickness on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug, the second thickness being smaller than the first thickness.

公开(公告)号：US20250081483A1

公开(公告)日：2025-03-06

申请号：US18636601

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeseul LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Jinwook LEE

IPC: H10B12/00

Abstract: An integrated circuit device includes a lower electrode, a dielectric film covering the lower electrode, an upper electrode covering the dielectric film, and a multilayered interface structure between the dielectric film and the upper electrode, wherein the multilayered interface structure includes a transition metal-aluminum (Al) complex oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al complex oxide layer being in contact with the dielectric film, and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al complex oxide layer.

公开(公告)号：US20250081431A1

公开(公告)日：2025-03-06

申请号：US18809483

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Jongyeong MIN ,  Kyooho JUNG ,  Joonsuk PARK ,  Jiye BAEK ,  Yeseul LEE

IPC: H10B12/00

Abstract: An integrated circuit device comprising; a transistor on a substrate, and a capacitor structure electrically connected to the transistor. The capacitor structure includes a lower electrode, a lower interface film on the lower electrode, a capacitor dielectric film on the lower interface film, an upper interface film on the capacitor dielectric film, and an upper electrode on the upper interface film. The lower interface film includes a first lower interface layer including metal oxide doped with an impurity, a second lower interface layer including a material that is substantially the same as a material of the first lower interface layer and doped with nitrogen, and a third lower interface layer including a material that is identical to a material of the capacitor dielectric film and doped with nitrogen, the first to third lower interface layers being sequentially stacked on the lower electrode, and wherein the upper interface film includes a first upper interface layer including metal oxide, a second upper interface layer including a material that is identical to a material of the first upper interface layer and doped with nitrogen, and a third upper interface layer including a material that is identical to the material of the capacitor dielectric film and doped with nitrogen, the first to third upper interface layers being sequentially stacked on the upper electrode.

公开(公告)号：US20230205427A1

公开(公告)日：2023-06-29

申请号：US17982951

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Heeseok EUN

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0673 ,  G06F3/0659

Abstract: Provided is an operating method of a storage device including a memory controller and a memory device, the operating method including storing a plurality of streams received from a host in the memory device; performing a management operation on a first storage region of the memory device in which a first stream from among the plurality of streams is stored; and performing a management operation on a second storage region of the memory device in which a second stream selected from among the plurality of streams based on an attribute of the first stream is stored.