公开(公告)号：US20210193678A1

公开(公告)日：2021-06-24

申请号：US16926045

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

公开(公告)号：US12133384B2

公开(公告)日：2024-10-29

申请号：US18352182

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US12010849B2

公开(公告)日：2024-06-11

申请号：US17934959

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H10B43/27 ,  H01L21/762 ,  H01L23/48 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B41/49 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L23/528 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

公开(公告)号：US11737270B2

公开(公告)日：2023-08-22

申请号：US17897255

申请日：2022-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US11678489B2

公开(公告)日：2023-06-13

申请号：US17532271

申请日：2021-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon

IPC: H01L23/528 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556

Abstract: A three-dimensional flash memory device including a lower and upper word line stack; a cell channel structure; and a dummy channel structure, wherein the cell channel structure includes a lower cell channel structure; an upper cell channel structure; and a cell channel enlarged portion between the lower and upper cell channel structures and having a width greater than that of the lower cell channel structure, wherein the dummy channel structure includes a lower dummy channel structure; an upper dummy channel structure; and a dummy channel enlarged portion between the lower and upper dummy channel structures, the dummy channel enlarged portion having a width greater than that of the lower dummy channel structure, wherein a difference between the width of the dummy channel enlarged portion and the lower dummy channel structure is greater than a difference between the width of the cell channel enlarged portion and the lower cell channel structure.

公开(公告)号：US11508744B2

公开(公告)日：2022-11-22

申请号：US16903990

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisung Cheon ,  Kiyoon Kang

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11582 ,  H01L29/792

Abstract: A memory device may include a substrate; a first stack structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stack structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure penetrating the first stack structure and the second stack structure, wherein the channel structure comprises a first portion in a first channel hole penetrating the first stack structure, a second portion in a second channel hole penetrating the second stack structure, and a first protrusion located in a first recess recessed into one layer of the plurality of first interlayer insulating layers from a side portion of the first channel hole.

公开(公告)号：US11917819B2

公开(公告)日：2024-02-27

申请号：US17359771

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Geunwon Lim ,  Jisung Cheon

IPC: H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L21/311

CPC classification number: H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L21/31111 ,  H01L21/31116

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US20230363157A1

公开(公告)日：2023-11-09

申请号：US18352182

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/40 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US11600632B2

公开(公告)日：2023-03-07

申请号：US16752141

申请日：2020-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

公开(公告)号：US20230032392A1

公开(公告)日：2023-02-02

申请号：US17934959

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/48

Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.