公开(公告)号：US20240014166A1

公开(公告)日：2024-01-11

申请号：US18218886

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Jaechoon KIM ,  Taehwan KIM ,  Kyungsuk OH ,  Heejung Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/05647 ,  H01L2224/80359 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/06505 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32013 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80357 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9222

Abstract: A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.

公开(公告)号：US20240413038A1

公开(公告)日：2024-12-12

申请号：US18402558

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Jae Choon KIM ,  Sunggu KANG ,  Taehwan KIM

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A stacked semiconductor package includes: a first semiconductor package that includes a first region and a second region and includes a semiconductor chip including a first element at the first region and a second element at the second region; a second semiconductor package on the first region of the first semiconductor package; and a member for heat dissipation at the second region of the first semiconductor package and overlapping at least a portion of the second element in a vertical direction perpendicular to an in-plane direction of the first semiconductor package.

公开(公告)号：US20240145360A1

公开(公告)日：2024-05-02

申请号：US18244997

申请日：2023-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo PARK ,  Jaechoon KIM ,  Sunggu KANG ,  Eunho CHO ,  Taehwan KIM ,  Jonggyu LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/1434

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings, a first semiconductor chip on the first redistribution wiring layer and having a first thickness from the first redistribution wiring layer, a second semiconductor chip disposed on the first redistribution wiring layer spaced apart from the first semiconductor chip and having a second thickness from the first redistribution wiring layer smaller than the first thickness, a sealing member covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer, a plurality of conductive vias provided in the sealing member and electrically connected to the first redistribution wirings, a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the conductive vias, and at least one third semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings.

公开(公告)号：US20230307318A1

公开(公告)日：2023-09-28

申请号：US18066861

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggyu LEE ,  Sunggu KANG ,  Jaechoon KIM ,  Taehwan KIM ,  Hwanjoo PARK ,  Kyungsuk OH

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/473 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/3128

Abstract: A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.

公开(公告)号：US20220353417A1

公开(公告)日：2022-11-03

申请号：US17732976

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwajoong JUNG ,  Bongchan KIM ,  Kwangseok BYON ,  Taehwan KIM ,  Hyungjin RHO ,  Jaeheung PARK ,  Jonghun WON

IPC: H04N5/232 ,  H05K1/14 ,  H05K1/11 ,  H04N5/225

Abstract: Disclosed is an electronic device including a camera module enabling a movable member (e.g., a circuit board) having an image sensor disposed thereon to move for an image stabilization function and including a connecting member that provides electrical connection of the image sensor, and an electronic device including the camera module.

公开(公告)号：US20210251083A1

公开(公告)日：2021-08-12

申请号：US17172338

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwajoong JUNG ,  Manho KIM ,  Taehwan KIM ,  Kihuk LEE ,  Yonghwan CHOI

IPC: H05K3/12 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: An electronic device includes: a housing and a printed circuit board (PCB) structure disposed in the housing. The PCB structure includes a circuit board including an opening area formed through a first surface of the circuit board and a second surface of the circuit board opposite the first surface and a conductive pattern formed in a peripheral area around the opening area, a plate disposed on the second surface of the circuit board covering the opening area, an electronic element disposed on the plate and electrically connected with the circuit board, a resin portion disposed between the plate and the circuit board and extending from the conductive pattern, the resin portion including a conductive material, and a solder portion formed between the resin portion and the plate.

公开(公告)号：US20240348907A1

公开(公告)日：2024-10-17

申请号：US18752312

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosang AN ,  Hwajoong JUNG ,  Beomsik KIM ,  Bongchan KIM ,  Taehwan KIM ,  Hyungjin RHO ,  Jaeheung PARK ,  Kwangseok BYON ,  Jonghoon WON

IPC: H04N23/55 ,  H04N23/54

CPC classification number: H04N23/55 ,  H04N23/54

Abstract: A camera module according to various embodiments of the disclosure may include: an image sensor (140); a substrate (110) electrically connected to the image sensor (140); a bracket (120) configured to fix the substrate (110); and a plate (130) disposed on the bracket (120) such that the width (131) of a surface of the plate (130) facing the image sensor (140) includes the width (141) of an area in which the image sensor (140) is disposed, thereby shielding at least a part of a space in which the image sensor (140) is disposed from the outside, wherein the bracket (120) may be formed by injection molding a material forming the bracket (120) in a state in which the plate (130) is inserted into a mold. Various other embodiments inferable from the specification are also possible

公开(公告)号：US20240186290A1

公开(公告)日：2024-06-06

申请号：US18236024

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan KIM ,  Youngdeuk KIM ,  Jaechoon KIM ,  Kyungsuk OH ,  Jonggyu LEE ,  Mina CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.

公开(公告)号：US20240048835A1

公开(公告)日：2024-02-08

申请号：US18491143

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan KIM ,  Bongchan KIM ,  Hwajoong JUNG ,  Hyungjin RHO ,  Jaeheung PARK ,  Kwangseok BYON ,  Hyosang AN ,  Jaehyoung PARK ,  Kihuk LEE

IPC: H04N23/55 ,  H04M1/02 ,  H04N23/54

CPC classification number: H04N23/55 ,  H04M1/0264 ,  H04M1/0277 ,  H04N23/54 ,  H04M2250/52

Abstract: According to various embodiments disclosed herein, a camera module and/or an electronic device including same comprises: a lens assembly including at least one lens aligned on an optical axis; a first circuit board that includes an image sensor disposed on the optical axis and is disposed to be movable along two intersecting directions on a plane perpendicular to the optical axis; a second circuit board in which at least one connector is disposed; and a flexible printed circuit board electrically connecting the first circuit board and the second circuit board. The flexible printed circuit board includes: a first end coupled to the first circuit board; a second end coupled to the second circuit board; a plurality of extensions extending from the first end and connected to the second end; at least one slit disposed between two adjacent extensions among the plurality of extensions; and a plurality of conducting wires arranged in the plurality of extensions, wherein two or more conducting wires selected from among the conducting wires and arranged in different extensions can be connected in parallel.

公开(公告)号：US20230170304A1

公开(公告)日：2023-06-01

申请号：US18095900

申请日：2023-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Taehwan KIM ,  Hyunjung SONG ,  Hyoeun KIm ,  Wonil LEE ,  Sanguk HAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5384 ,  H01L24/14 ,  H01L23/367 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.