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    Semiconductor doped region with biased isolated members
    11.
    发明授权
    Semiconductor doped region with biased isolated members 有权

    公开(公告)号：US12211807B2

    公开(公告)日：2025-01-28

    申请号：US18490866

    申请日：2023-10-20

    Applicant: Texas Instruments Incorporated

    Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

    IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

    Fail-open isolator
    12.
    发明授权
    Fail-open isolator 有权

    公开(公告)号：US12183672B2

    公开(公告)日：2024-12-31

    申请号：US17677729

    申请日：2022-02-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Vinod Rai ,  Yogesh Ramadass ,  Anant Kamath ,  Kashyap Barot

    IPC: H01L23/525 ,  H02H3/04

    Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

    GATE STRUCTURE OF SEMICONDUCTOR DEVICE
    14.
    发明申请
    GATE STRUCTURE OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250107131A1

    公开(公告)日：2025-03-27

    申请号：US18472329

    申请日：2023-09-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sandeep R. Bahl ,  Ujwal Radhakrishna ,  Chang Soo Suh

    IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66

    Abstract: The present disclosure generally relates to a conductive layer in a gate structure of a semiconductor device. The conductive layer may be a silicon layer. An example is a semiconductor device. The semiconductor device includes a channel layer, a barrier layer, a gate layer, and a silicon layer. The channel layer is over a semiconductor substrate. The barrier layer is over the channel layer. The gate layer is over the barrier layer. The silicon layer is over and contacts the gate layer.

    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE
    15.
    发明申请
    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE 有权

    公开(公告)号：US20240405078A1

    公开(公告)日：2024-12-05

    申请号：US18326698

    申请日：2023-05-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Johan Strydom ,  Zhikai Tang ,  Dong Seup Lee

    IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

    Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

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