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    WAFER POD HANDLING METHOD
    11.
    发明申请
    WAFER POD HANDLING METHOD 审中-公开

    公开(公告)号：US20200098613A1

    公开(公告)日：2020-03-26

    申请号：US16677626

    申请日：2019-11-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

    IPC: H01L21/677

    Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

    Method of trimming fin structure
    15.
    发明授权
    Method of trimming fin structure 有权
    修剪翅片结构的方法

    公开(公告)号：US09412850B1

    公开(公告)日：2016-08-09

    申请号：US14597700

    申请日：2015-01-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Sheng Chuang ,  You-Hua Chou

    IPC: H01L21/82 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/84

    CPC classification number: H01L29/66818 ,  H01L21/30608 ,  H01L21/3085 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/66795

    Abstract: A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure cladding the fin structure, in which the epitaxy structure has a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110); and (iii) removing the epitaxy structure and a portion of the fin structure to obtain a trimmed fin structure.

    Abstract translation: 修整翅片结构的方法包括以下操作：（i）在基板上形成翅片结构; （ii）外延生长包覆鳍结构的外延结构，其中外延结构具有具有米勒指数（111）的第一晶格面，具有米勒指数（100）的第二晶格面和具有米勒指数（110）的第三晶格面 ）; 和（iii）去除外延结构和鳍结构的一部分以获得修剪的翅片结构。

    Mechanisms for controlling gas flow in enclosure
    16.
    发明授权
    Mechanisms for controlling gas flow in enclosure 有权
    控制外壳气体流动的机理

    公开(公告)号：US09272315B2

    公开(公告)日：2016-03-01

    申请号：US14051532

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： You-Hua Chou ,  Kuo-Sheng Chuang ,  Yii-Cheng Lin

    IPC: B08B17/00 ,  B01D46/44 ,  F24F3/16 ,  H01L21/67

    CPC classification number: B08B17/00 ,  B01D46/442 ,  B01D46/446 ,  B01D2258/0216 ,  B01D2279/51 ,  F24F3/1607 ,  H01L21/67017

    Abstract: Embodiments of mechanisms for controlling a gas flow in an interface module are provided. A method for controlling a gas flow in an enclosure includes providing the enclosure which is capable of containing a substrate. The method also includes providing a gas into the enclosure. The method further includes cleaning the gas. In addition, the method includes actuating the gas to generate the gas flow, and the gas flow passes through the substrate when the substrate is located in the enclosure.

    Abstract translation: 提供了用于控制接口模块中的气流的机构的实施例。 用于控制外壳中的气流的方法包括提供能够容纳基底的外壳。 该方法还包括将气体提供到外壳中。 该方法还包括清洁气体。 此外，该方法包括致动气体以产生气流，并且当衬底位于外壳中时气体流过衬底。

    Method of patterning material layer
    17.
    发明授权
    Method of patterning material layer 有权

    公开(公告)号：US11367616B2

    公开(公告)日：2022-06-21

    申请号：US16931459

    申请日：2020-07-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： You-Hua Chou ,  Kuo-Sheng Chuang

    IPC: H01L21/033 ,  H01L21/3213

    Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.

    SEMICONDUCTOR PROCESSING STATION
    19.
    发明申请
    SEMICONDUCTOR PROCESSING STATION 审中-公开

    公开(公告)号：US20190311930A1

    公开(公告)日：2019-10-10

    申请号：US16449452

    申请日：2019-06-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

    IPC: H01L21/677

    Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

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