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    Manufacturing method of semiconductor device
    12.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US09466484B1

    公开(公告)日：2016-10-11

    申请号：US14859491

    申请日：2015-09-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Yu-Ting Li ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Wu-Sian Sie ,  I-Lun Hung ,  Chun-Tsen Lu ,  Shih-Ming Lin ,  Lan-Ping Chang

    IPC: H01L21/31 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11

    CPC classification number: H01L27/11 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/1116

    Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

    Abstract translation: 提供一种半导体器件的制造方法。 该制造方法包括以下步骤。 在基板的第一区域和第二区域中形成多个翅片结构。 第一区域中的翅片结构的第一密度低于第二区域中的翅片结构的第二密度。 栅极电介质层形成在鳍结构上。 在第一区域和第二区域中的栅介质层和鳍结构上形成非晶硅层。 设置在第一区域中的非晶硅层的一部分被退火以通过激光形成晶体硅层。 设置在第一区域中的结晶硅层和设置在第二区域中的非晶硅层被抛光。

    Fabricating method of transistors without dishing occurred during CMP process
    13.
    发明授权
    Fabricating method of transistors without dishing occurred during CMP process 有权

    公开(公告)号：US11257711B1

    公开(公告)日：2022-02-22

    申请号：US17023391

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02

    Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

    PLANARIZATION METHOD
    15.
    发明申请
    PLANARIZATION METHOD 审中-公开

    公开(公告)号：US20180197749A1

    公开(公告)日：2018-07-12

    申请号：US15862564

    申请日：2018-01-04

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Fu-Shou Tsai ,  Wen-Chin Lin ,  Chun-Liang Liu

    IPC: H01L21/321 ,  H01L27/108 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3105

    Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160300765A1

    公开(公告)日：2016-10-13

    申请号：US14682265

    申请日：2015-04-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

    IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

    CPC classification number: H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

    Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

    Abstract translation: 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    20.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250169079A1

    公开(公告)日：2025-05-22

    申请号：US18404839

    申请日：2024-01-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Chau-Chung Hou ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ren-Peng Huang ,  Ching-Yang Chuang

    IPC: H10B61/00

    Abstract: A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

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