公开(公告)号：US20180286872A1

公开(公告)日：2018-10-04

申请号：US15498464

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Hsueh-Hao Shih

IPC: H01L27/11 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/417

Abstract: A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.

公开(公告)号：US20140035111A1

公开(公告)日：2014-02-06

申请号：US14062914

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Meng-Ping Chuang ,  Yu-Tse Kuo ,  Chia-Chun Sun ,  Yun-San Huang

IPC: H01L29/06

CPC classification number: H01L29/0692 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0684

Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Abstract translation: 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外，梳状掺杂区域和鱼骨形掺杂区域是交错的。