公开(公告)号：US11881493B2

公开(公告)日：2024-01-23

申请号：US17990755

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen

IPC: H01L27/146 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L27/14612 ,  H01L23/53295 ,  H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4933 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/41725 ,  H01L29/665

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.

公开(公告)号：US11538844B2

公开(公告)日：2022-12-27

申请号：US16794233

申请日：2020-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen

IPC: H01L27/146 ,  H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer, first self-aligned silicide layer on the polysilicon plug and first conductive metal layer on the first self-aligned silicide layer; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in first ILD layer, second self-aligned silicide layer on the second polysilicon plug, and second conductive metal layer on the second self-aligned silicide layer.

公开(公告)号：US10134744B1

公开(公告)日：2018-11-20

申请号：US15681444

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Han Chen ,  Wei-Chi Chen ,  Ching Chang ,  Ming-Shing Chen ,  Chao-Hsien Wu ,  Chia-Hui Hwang ,  Lu-Ran Huang

IPC: G11C11/404 ,  H01L27/11 ,  H01L27/12 ,  G11C11/4097 ,  G11C11/417

Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

公开(公告)号：US09461166B2

公开(公告)日：2016-10-04

申请号：US14071674

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen ,  Wei-Ting Wu ,  Ming-Hui Chang ,  Chao-Chun Ning

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/1083 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

Abstract translation: 提供了包括衬底，第二深阱，栅极，源极，漏极和第一掺杂剂区域的横向扩散的金属氧化物半导体器件。 衬底包括具有第一导电类型的第一深阱。 具有第二导电类型的第二深阱设置在第一深孔中。 栅极设置在基板和第一和第二深井的边界上。 具有第二导电类型的源极和漏极分别设置在栅极旁边和第一深阱以及第二深阱的旁边。 具有第一导电类型的第一掺杂区域设置在第二深阱中，其中第一掺杂区域与漏极分离。 此外，还提供了制造所述横向扩散金属氧化物半导体器件的方法。