公开(公告)号：US20190221238A1

公开(公告)日：2019-07-18

申请号：US15900811

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ting-Hao Chang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shih-Hao Liang ,  Chun-Hsien Huang ,  Shu-Ru Wang ,  Hsin-Chih Yu

IPC: G11C5/02 ,  H01L27/108 ,  H01L27/105 ,  H01L27/11 ,  G11C11/409 ,  G11C11/419

CPC classification number: G11C5/02 ,  G11C11/409 ,  G11C11/419 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/1108 ,  H01L29/7869

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

公开(公告)号：US09947673B1

公开(公告)日：2018-04-17

申请号：US15479253

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Chia Chang ,  Shih-Hao Liang ,  Chun-Yen Tseng ,  Yu-Tse Kuo ,  Ching-Cheng Lung ,  Hung-Chan Lin ,  Shao-Hui Wu

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412 ,  H01L29/24

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/24

Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.