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23 records (took 0.02 seconds)

    13.
    发明专利
    未知

    公开(公告)号：DE3789199D1

    公开(公告)日：1994-04-07

    申请号：DE3789199

    申请日：1987-11-04

    Applicant: XILINX INC

    Inventor： HSIEH HUNG-CHENG

    IPC: H03K3/353 ,  H03K3/3565 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/185

    Abstract: A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage (29) and a reference voltage generator (20). In the TTL mode, the reference voltage generator (20) supplies a reference voltage (V REF) having a level that forces the trigger point of the Schmitt trigger (10) to a predetermined value. In the CMOS mode, the reference voltage generator (20) is disabled and a voltage equal to the power supply voltage (V cc) is provided to the Schmitt trigger (10). The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

    5-TRANSISTOR MEMORY CELL WITH KNOWN STATE ON POWER-UP
    14.
    发明专利
    5-TRANSISTOR MEMORY CELL WITH KNOWN STATE ON POWER-UP 未知

    公开(公告)号：CA1323928C

    公开(公告)日：1993-11-02

    申请号：CA595793

    申请日：1989-04-05

    Applicant: XILINX INC

    Inventor： HSIEH HUNG-CHENG

    IPC: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

    Abstract: A 5-TRANSISTOR MEMORY CELL WITH KNOWN STATE ON POWER-UP Hung-Cheng Hsieh A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

    5-TRANSISTOR MEMORY CELL WHICH CAN BE RELIABLY READ AND WRITTEN
    16.
    发明专利
    5-TRANSISTOR MEMORY CELL WHICH CAN BE RELIABLY READ AND WRITTEN 未知

    公开(公告)号：CA1260140A

    公开(公告)日：1989-09-26

    申请号：CA518484

    申请日：1986-09-18

    Applicant: XILINX INC

    Inventor： HSIEH HUNG-CHENG

    IPC: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412 ,  G11C11/24

    Abstract: A 5-TRANSISTOR MEMORY CELL WHICH CAN BE RELIABLY READ AND WRITTEN A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to read. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.

    18.
    发明专利
    未知

    公开(公告)号：DE69031525T2

    公开(公告)日：1998-01-29

    申请号：DE69031525

    申请日：1990-07-26

    Applicant: XILINX INC

    Inventor： FREEMAN ROSS H ,  HSIEH HUNG-CHENG

    IPC: H03K19/173 ,  H03K19/177

    Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells (C1,1,C1,2,...) which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

    LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY
    20.
    发明专利
    LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY 未知

    公开(公告)号：CA2037142C

    公开(公告)日：1996-05-07

    申请号：CA2037142

    申请日：1991-02-26

    Applicant: XILINX INC

    Inventor： HSIEH HUNG-CHENG ,  CARTER WILLIAM S ,  ERICKSON CHARLES R ,  CHEUNG EDMOND Y

    IPC: G06F7/50 ,  G06F7/506 ,  G06F7/57 ,  H03K19/01 ,  G06F7/48 ,  H03K19/20

    Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

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