公开(公告)号：JP2009267154A

公开(公告)日：2009-11-12

申请号：JP2008116053

申请日：2008-04-25

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： WANG CHIN-FA ,  CHEN CHIN-TI ,  YU BINGXUN ,  HSIEH WAN JUNG

IPC: H01L23/50 ,  H01L23/28 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/32245 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a lead-on paddle type semiconductor package wherein there is no problem in positional deviations and exposure of leads during molding operation and seal bubbles are not generated between the leads and a lead paddle.
SOLUTION: The lead-on paddle type semiconductor package includes: a first surface 111; a second surface 112 opposed to the first surface 111; leads 110 of a plurality of lead frames having a plurality of side faces 113 between the first surface 111 and the second surface 112; a first chip 120 stuck to the first surface 111; a lead paddle 130 having a putting surface 131 and an exposed surface 132; an adhesive 140 for sticking the putting surface 131 to the second surface 112 and covering the side faces 113 to combine the lead puddle 130 to the lead 110 group of the lead frames; and a sealing body 150 for sealing off the first chip 120, the adhesive 140, portions of the lead 110 group of the lead frames and portions of the paddle 130 and exposing the exposed surface 132.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供引导式桨式半导体封装，其中在成型操作期间引线的位置偏离和曝光没有问题，并且在引线和引线片之间不产生密封气泡。 引线式桨式半导体封装包括：第一表面111; 与第一表面111相对的第二表面112; 在第一表面111和第二表面112之间具有多个侧面113的多个引线框架的引线110; 粘附到第一表面111的第一芯片120; 具有放置表面131和暴露表面132的引导板130; 用于将放置表面131粘贴到第二表面112并覆盖侧面113以将引线熔池130组合到引线框架的引线110组的粘合剂140; 密封体150，用于密封第一芯片120，粘合剂140，引线框架的引线110组和桨叶130的部分的部分，并暴露暴露表面132.版权所有（C）2010， JPO和INPIT

公开(公告)号：JP2009200319A

公开(公告)日：2009-09-03

申请号：JP2008041506

申请日：2008-02-22

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： WANG CHIN-FA ,  HSIEH WAN JUNG ,  HSU YU-MEI

IPC: H01L23/50 ,  H01L23/28

CPC classification number: H01L2224/48091 ,  H01L2224/4826 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a lead frame which never causes a position shift due to inclination of a lead and improves wire bonding quality and adhesive strength of die attaching. SOLUTION: The lead frame 200 includes a plurality of leads 210, a branch piece 220, and a coupling bar 230, wherein the leads 210 is formed on a first plane 201 and the branch piece 220 is formed on a second plane 202, so that the branch piece 220 is lower, and a coupling bar 230 is formed between the first plane 201 and second plane 202. The coupling bar 230 has at least two or more folds, for example, a first fold 231A and a second fold 231B, and elastically couples the branch piece 220 and a circumferential lead 211. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种引线框架，其不会由于引线的倾斜而导致位置偏移，并且提高了引线接合质量和管芯附着的粘合强度。 引线框架200包括多个引线210，分支件220和联接杆230，其中引线210形成在第一平面201上，并且分支件220形成在第二平面202上 ，使得分支件220较低，并且联接杆230形成在第一平面201和第二平面202之间。联接杆230具有至少两个或更多个折叠，例如第一折叠231A和第二折叠 231B，并且弹性地联接分支件220和周向引线211.版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009117318A

公开(公告)日：2009-05-28

申请号：JP2007301572

申请日：2007-11-21

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： WU MING-YEN

IPC: H05B3/00

CPC classification number: F27B17/0025 ,  F27D7/04 ,  H01L21/67109

Abstract: PROBLEM TO BE SOLVED: To provide a method for raising temperature of a chamber, and its heating device.
SOLUTION: The method for raising the temperature of the chamber includes a process of heating air in the chamber, and a process of injecting dried air into the chamber to mix the injected air with hot air and exhausting wet air. At the same time, the heating device is provided to raise the temperature in the chamber in a short time, and the cost is effectively suppressed by creating an isothermal environment.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种室内温度升高的方法及其加热装置。 解决方案：用于提高室的温度的方法包括加热室中的空气的过程，以及将干燥空气注入室中以将注入的空气与热空气混合并排出湿空气的过程。 同时，提供加热装置以在短时间内提高室内的温度，并且通过产生等温环境有效地抑制了成本。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009054768A

公开(公告)日：2009-03-12

申请号：JP2007219683

申请日：2007-08-27

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： WU MING-YEN

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a jig for positioning a BGA package waiting for measurement.
SOLUTION: The general-purpose jig for positioning the BGA (Ball Grid Array) waiting for measurement mainly includes: a net-type substrate 110, a latch 120 and a plurality of pins 130. The net-type substrate 110 has an element storing hole 111 and a pressurizing/measuring surface 112. A plurality of positioning holes arranged in a matrix and at equal intervals are disposed in the element storing hole 111. The latch 120 holds the BGA package for arranging it in the net-type substrate 110 and adjusting a solder ball group to a part of or whole positioning hole groups by one to one. The pins elastically project to a periphery of the pressuring/measuring surface 112 of the net-type substrate 110. Thus, the general-purpose jig positions the BGA packages of various specifications irrespective of a substrate size, and the number and arrangement of solder balls.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于定位等待测量的BGA封装的夹具。 解决方案：用于定位等离子测量的BGA（球栅阵列）的通用夹具主要包括：网状基板110，闩锁120和多个销130.网状基板110具有 元件存储孔111和加压/测量表面112.在元件存储孔111中设置以矩阵形式排列的多个定位孔。闩锁120保持BGA封装以将其布置在网状基板 并且将焊球组调整到一个或多个定位孔组的一部分或全部。 销弹性地突出到网状基板110的加压/测量表面112的周边。因此，通用夹具定位各种规格的BGA封装，而与基板尺寸无关，并且焊球的数量和布置 。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009054684A

公开(公告)日：2009-03-12

申请号：JP2007218122

申请日：2007-08-24

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG ,  FANG LI-CHIH ,  IWATA TAKAO

IPC: H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/3677 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor POP device avoiding the rupture of a solder fine contact during semiconductor lamination.
SOLUTION: The semiconductor POP device 200 principally includes semiconductor packages 210 and 220 having a plurality of solder fine contacts and solder materials 230 for soldering and connecting the solder fine contacts. The semiconductor packages 210 and 220 have substrates 211 and 221 and chips 212 and 222 placed on the substrates, respectively. The solder fine contacts of the lower semiconductor package 210 are disposed at a plurality of upper-layer bumps 213 on a top surface 211A of the substrate 211, and the solder fine contacts of the upper semiconductor package 220 are disposed at a plurality of lower-layer bumps 223 on the reverse surface 221B of the substrate 221. The group of lower-layer bumps 223 are aligned with the group of upper-layer bumps 213 so that the group of upper-layer bumps 213 and the group of lower-layer bumps 223 are joined together with the solder materials 230, and they are equally soldered together.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种避免在半导体层叠期间焊料细微接触破裂的半导体POP器件。 解决方案：半导体POP器件200主要包括具有多个焊料细小触点的半导体封装210和220以及用于焊接和连接焊料细微触点的焊接材料230。 半导体封装210和220分别具有放置在基板上的基板211和221以及芯片212和222。 下部半导体封装210的焊料细小的触点设置在基板211的上表面211A上的多个上层凸起213上，并且上部半导体封装220的焊料细小触点设置在多个较低层 基板221的背面221B上的层叠凸点223.下层凸块223的组与上层凸块213组对准，使得上层凸块213和下层凸块组 223与焊接材料230连接在一起，并且它们被同等焊接在一起。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008277660A

公开(公告)日：2008-11-13

申请号：JP2007121795

申请日：2007-05-02

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HONG JIATOU ,  LU ZHAOXIANG ,  QIU ZHENGXIAN

IPC: H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an LGA mounting-type electronic product which can avoid scratches and collisions of a metal pad group or a solder bonding layer.
SOLUTION: An LGA semiconductor mounting structure 200 is provided with a substrate 210, a chip 220, the solder bonding layer 230 and a foot stand 240. The substrate 210 has an upper surface 211 and a lower surface 212. A plurality of metal pads 213 are arranged on the lower surface 212 into an array shape. The chip 220 is installed on the upper surface 211 of the substrate 210 and is electrically connected to the metal pads 213. The solder bonding layer 230 is arranged in the metal pad group 213 and has first thickness which slightly projects to the lower surface 212 of the substrate 210. The foot stand 240 is disposed below the substrate 210 and has second thickness projecting to the lower surface 212 of the substrate, and Second thickness becomes thicker than first thickness.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够避免金属焊盘组或焊料接合层的划伤和碰撞的LGA安装型电子产品。 解决方案：LGA半导体安装结构200设置有基板210，芯片220，焊接接合层230和脚架240.基板210具有上表面211和下表面212.多个 金属焊盘213布置在下表面212上成阵列形状。 芯片220安装在基板210的上表面211上并与金属焊盘213电连接。焊接接合层230布置在金属焊盘组213中，并且具有稍微突出到下表面212的第一厚度 基座210.脚架240设置在基板210的下方，并具有向基板的下表面212突出的第二厚度，第二厚度变得比第一厚度厚。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008235661A

公开(公告)日：2008-10-02

申请号：JP2007074633

申请日：2007-03-22

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HSU HUNG-HSIN ,  YU CHI-CHUNG

IPC: H05K1/16 ,  H01L23/12

CPC classification number: H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a shared-substrate that can substantially shorten the amount of time required for re-designing and manufacturing substrate wiring. SOLUTION: The shared-substrate has multiple inscribed pads 311, 312 and 313 and circumscribed pads 321, 322 and 323, wherein all the inscribed pads 311, 312 and 313 are electrically connected to the cluster of the circumscribed pads 321, 322 and 323, and to allow a fuse to be blown arbitrarily, multiple branched interconnections 330 and multiple fuses F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11 and F12 serially connected to these branched interconnections 330 are formed on one surface of the substrate. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供可以显着缩短重新设计和制造衬底布线所需的时间量的共享衬底。 共享衬底具有多个内接垫311,312和313以及外接垫321,322和323，其中所有内接垫311,312和313电连接到外接垫321,322的簇 并且为了允许保险丝熔断，多个分支互连330和串联连接到这些分支互连330的多个保险丝F1，F2，F3，F4，F5，F6，F7，F8，F9，F10，F11和F12 形成在基板的一个表面上。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008177345A

公开(公告)日：2008-07-31

申请号：JP2007009173

申请日：2007-01-18

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG ,  KO KINKEI

IPC: H01L23/28 ,  H01L23/12

CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a BGA type package structure for preventing oveflow of mold sealant. SOLUTION: The BGA type package structure includes a substrate 310 having an upper surface 311, a lower surface 312, and a hole, a chip 320 mounted on the upper surface 311 and having a plurality of bonding pads for aligning the hole, a plurality of bonding wires for connecting a bonding pad group electrically with the substrate 310 through the hole, a mold sealant 340 having a right cube 341 formed on the upper surface 311 and sealing the chip 320 hermetically and at least one long cube 342 formed in the hole 313 and at a part of the lower surface 312 and sealing the bonding pad group hermetically, and a plurality solder balls 350 arranged on the lower surface 312 wherein a small mouth 316 is formed closely to the hole on the substrate 310 and since the diameter of the small mouth 316 becomes narrower than the average diameter of the hole, speed of the mold sealant 340 flowing around the hole can be moderated. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于防止模具密封剂溢出的BGA型封装结构。 解决方案：BGA型封装结构包括具有上表面311，下表面312和孔的基板310，安装在上表面311上的芯片320，并具有用于对准孔的多个焊盘， 用于通过孔与基板310电连接接合焊盘组的多个接合线，具有形成在上表面311上的右侧立方体341并密封芯片320的模具密封剂340以及至少形成在其中的至少一个长立方体342 孔313和下表面312的一部分并且密封粘合垫组，以及布置在下表面312上的多个焊球350，其中小口316紧密地形成在衬底310上的孔上，并且由于 小口316的直径变得比孔的平均直径变窄，可以缓和围绕孔的模具密封剂340的速度。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2020092249A

公开(公告)日：2020-06-11

申请号：JP2019114484

申请日：2019-06-20

Applicant: POWERTECH TECHNOLOGY INC

Inventor： MO CHU YUAN

IPC: H01L21/66 ,  G01R31/26 ,  G01R31/28

Abstract: 【課題】自動テスト設備における異常テスト信号チャネルの検出方法を提供する。【解決手段】本発明の検出方法では、まず原始テストデータを取得し且つマッピングデータに基づいて原始テストデータを複数のデータグループに区分し、同一のデータグループに含まれるテストデータは、同一のプローブグループによるテストで生成されたものである。次に、各データグループの歩留りを推定し、歩留りが第1不良閾値にマッチする場合、ウェハの歩留りを更に推定する。ウェハの歩留りが第2不良閾値にマッチしないか又は正常閾値にマッチする場合、異常であるテスト信号チャネルが決定される。自動テスト設備の従来のテスト手順に本発明に係る検出方法を適用することで、テストデータマップ上の不良カラーが付されたブロックは異常なテスト信号チャネルによるものであることを容易に認識可能である。【選択図】図6A

公开(公告)号：JP2020092247A

公开(公告)日：2020-06-11

申请号：JP2019008247

申请日：2019-01-22

Applicant: POWERTECH TECHNOLOGY INC

Inventor： SONG CHENG-HUNG ,  TSENG SHENG-TOU ,  CHEN BING GU ,  LIN CHIA-WEI ,  LIU JIN CHENG ,  TSENG JENTUNG ,  CHUANG MU-CHIN ,  XU KUN JI ,  WU QIN DA

IPC: H01L21/52 ,  H01L21/677 ,  H01L21/683

Abstract: 【課題】移動中にチップの表面に作用する力によるチップの異常又は破損を防止できるチップ移動設備及びその調整方法を提供する。【解決手段】チップ移動設備は、固定機械と、荷重センサが設けられたマニピュレータとを備えている。チップが固定機械から離れるように移動される過程における力対時間のグラフを荷重センサによって取得することができ、該力対時間のグラフを用いてチップ移動設備の部品を調整することができる。これにより、様々なチップについてこれを固定機械から離れるように移動するための最適な部品とパラメータの組み合わせを見つけ出すことができるため、バッチ生産時における、固定機械から離れるように移動される過程でのチップの異常又は破損を防止することができる。【選択図】図4