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11.发明专利
公开(公告)号：JP2004234659A
公开(公告)日：2004-08-19
申请号：JP2004019256
申请日：2004-01-28
Applicant: Schlumberger Malco Inc , Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc , シュルンベルジェ マルコ, インコーポレイテッドSchlumberger Malco, Inc.
Inventor： LEYDIER ROBERT ANTOINE , POMET CHRISTOPHE ALAIN
CPC classification number: G06F1/04
Abstract: PROBLEM TO BE SOLVED: To generate a reference clock by using a downstream reception USB signal transmitted by a host computer or a hub. SOLUTION: A USB device having a free-running oscillator generates a local clock signal in response to a signal on a universal serial bus (USB). The oscillator is substantially stable and operates at a frequency known for substantial incorrectness. A single end bit serial signal is extracted from a reception signal transmitted by a USB host computer or a hub, and a timing signal is activated by responding to it. A bit pattern is detected and intervals are measured in the single end bit serial signal, and the timing signal is activated in that period. A period P of the local clock signal is adjusted in response to one of the measured intervals. COPYRIGHT: (C)2004,JPO&NCIPI
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12.发明专利
公开(公告)号：JP2004171573A
公开(公告)日：2004-06-17
申请号：JP2003389690
申请日：2003-11-19
Inventor： PARTHASARATHY SIVAGNANAM , DRIKER ALEXANDER
CPC classification number: G06F9/3885 , G06F9/30043 , G06F9/30072
Abstract: PROBLEM TO BE SOLVED: To provide an improved technique for extending or alternating a processor instruction set architecture. SOLUTION: The processor architecture uses a split-instruction transaction so as to supply an extension unit with an operand and an instruction and to retrieve results from the extension unit and supports an electrical interface for coupling a processor core to one or more than one coprocessor extension units executing a computational instruction. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow a new computational instruction to be introduced without regeneration of the processor architecture. Support for a plurality of extension units and/or a plurality of execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within the extension units, extension instruction predicates, and for handling result save/restore on the processor core install and the interrupt is included. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2004165663A
公开(公告)日：2004-06-10
申请号：JP2003380089
申请日：2003-11-10
Inventor： ZHOU TIAO
IPC: G06K19/077 , G06K9/00 , H01L21/58 , H01L23/58 , H01L25/065 , H01L25/07 , H01L25/18
CPC classification number: G06K9/0002 , H01L23/573 , H01L24/48 , H01L24/83 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/73265 , H01L2224/83192 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , Y10T29/49128 , Y10T29/4913 , Y10T29/49146 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide an improved packaging technique for integrated circuits. SOLUTION: The device comprises a substrate 102, which is equipped with first integrated circuits 104, 106 and components for electronic circuit 108, 110, a first sealing structure 114 for sealing the first integrated circuits, a second integrated circuit 120 attached to the first sealing formation, and a second sealing structure 122 which seals at least a part of the first sealing formation, the first integrated circuits and a electronic component 112. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：为集成电路提供改进的封装技术。 解决方案：该装置包括衬底102，衬底102配备有第一集成电路104,106和用于电子电路108,110的部件，用于密封第一集成电路的第一密封结构114，连接到第一集成电路120的第二集成电路120 第一密封结构，以及密封第一密封结构，第一集成电路和电子部件112的至少一部分的第二密封结构122.权利要求（C）2004，JPO
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公开(公告)号：JP2004164622A
公开(公告)日：2004-06-10
申请号：JP2003354533
申请日：2003-10-15
Inventor： PARTHASARATHY SIVAGNANAM , COFLER ANDREW , CHAVEROT LIONEL
CPC classification number: G06F9/381 , G06F9/30181 , G06F9/325 , G06F9/3875 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02D10/13
Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of cache access in a processor without substantially degrading performance.
SOLUTION: For instruction clusters for which no significant performance penalty such as execution of hardware loops is incurred, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, in the case that instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for remaining iterations of the hardware loop to further reduce power consumption.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2004125791A
公开(公告)日：2004-04-22
申请号：JP2003334020
申请日：2003-09-25
Inventor： DANIEL A THOMAS , DEBEURRE BRUNO J , THOMA PETER J
IPC: G01B7/28 , G01N27/414 , G01N33/487 , G06K9/00 , G06T1/00 , H01L51/05 , H01L51/00
CPC classification number: G01L1/146 , G01L1/148 , G01N27/4145 , G01N27/4148 , G06K9/0002 , H01L27/307 , H01L51/0508
Abstract: PROBLEM TO BE SOLVED: To provide a sensor device manufactured using an organic semiconductor material. SOLUTION: Sensor cells are arranged in the form of an array within an organic semiconductor layer. A row and column selection circuit addresses one cell of the array at a time to determine the presence of an object contacting or located in proximity to a detection surface above each cell, e.g., the protruding or recessed part of a fingerprint. A control circuit can be provided inside either a companion silicon chip or a second layer made from an organic semiconductor material in order to communicate with the array and an associated system processor. The array consisting of the sensor cells can be manufactured using a flexible polymer substrate. The substrate is peeled and disposed of after contacts are patterned on the organic semiconductor layer. The organic semiconductor layer is usable together with a reactive interface layer which is made redundant to detect a specific chemical material in a test medium. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：提供使用有机半导体材料制造的传感器装置。 传感器单元以有机半导体层内的阵列的形式排列。 行和列选择电路一次寻址阵列的一个单元，以确定接触或位于每个单元上方的检测表面附近的物体的存在，例如指纹的突出或凹入部分。 控制电路可以设置在伴随硅芯片或由有机半导体材料制成的第二层内，以便与阵列和相关系统处理器通信。 由传感器单元组成的阵列可以使用柔性聚合物基底制造。 在有机半导体层上图案化触点之后，剥离基板并进行处置。 有机半导体层与反应性界面层一起使用，其被制成多余的以检测测试介质中的特定化学材料。 版权所有（C）2004，JPO
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Patent Agency Ranking
公开(公告)号：JP2004064093A
公开(公告)日：2004-02-26
申请号：JP2003280819
申请日：2003-07-28
Inventor： HARRY MICHAEL SIEGEL
CPC classification number: H01L23/36 , H01L23/3121 , H01L23/4006 , H01L23/4093 , H01L2023/4043 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/83191 , H01L2224/83192 , H01L2924/1815
Abstract: PROBLEM TO BE SOLVED: To provide an improved technology to remove heat from an active area of an integrated circuit device. SOLUTION: The method for removing heat from the active area 104 of the integrated circuit device is provided. A separating body 112 is imparted to the active area 104 of the integrated circuit device. A heat-conductive element 102 is joined to the active area 104 of the integrated circuit device on the outside of the separating body 112. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2003332945A
公开(公告)日：2003-11-21
申请号：JP2003129280
申请日：2003-05-07
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： CERVINI STEFANO
IPC: H04B1/707
CPC classification number: H04B1/7115 , H04B2201/70707
Abstract: PROBLEM TO BE SOLVED: To improve a rake receiver used when spread-spectrum signal is demodulated.
SOLUTION: An architecture for a rake receiver of a CDMA demodulator utilizes a common data path for signal processing. This common data bus is shared by all channels (either physical channels or propagation paths within physical channels) to avoid redundant calculations, reduce circuit space, and reduce power consumption. The sharing of the common data path for demodulation is made in a time division manner, with each channel being given sequential access to the data bus to perform all or part of a given function (for example, de-scramble, de-spreading, de-rotating, and de-skewing accumulation).
COPYRIGHT: (C)2004,JPOAbstract translation: 要解决的问题：改进扩频信号解调时使用的耙式接收机。 解决方案：用于CDMA解调器的瑞克接收机的架构利用公共数据路径进行信号处理。 该公共数据总线由所有通道（物理通道中的物理通道或传播路径）共享，以避免冗余计算，减少电路空间并降低功耗。 以时分方式共享用于解调的公共数据路径，其中每个信道被给予对数据总线的顺序访问以执行给定功能的全部或部分（例如，去加扰，解扩，de 旋转和反倾销积累）。 版权所有（C）2004，JPO
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18.发明专利Method and system for 3d smoothing within bound of error region of matching curve 审中-公开用于匹配曲线的错误区域中的3D平滑的方法和系统
公开(公告)号：JP2003317117A
公开(公告)日：2003-11-07
申请号：JP2003114254
申请日：2003-04-18
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： NG KIM CHAI
CPC classification number: G06K9/20 , G06K2209/40 , G06T7/55
Abstract: PROBLEM TO BE SOLVED: To provide an improved image processing system and a method to remove and smooth out irregularities from a 3D image representation from multiple 2D image views. SOLUTION: The image processing system and the method are provided to remove and smooth out irregularities from 3D image information reproduced from one scene, specially, multiple 2D image views from a uniform surface of an object in the scene. In this method, a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene is defined. Each pixel is associated with predefined 3D depth information and further associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. An average 3D depth information associated with the plurality of pixels overlapped by the window is calculated and if the calculated average 3D depth information is within an error region of the matching curve associated with the subject pixel, the calculated average 3D depth information is assigned to the 3D depth information of the subject pixel. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：提供一种改进的图像处理系统和从多个2D图像视图中去除和平滑来自3D图像表示的不规则的方法。
解决方案：提供图像处理系统和方法，以从一个场景再现的3D图像信息中去除和平滑不规则，特别是来自场景中物体的均匀表面的多个2D图像视图。 在该方法中，定义与场景的多个2D图像视图中的一个的多个像素重叠的窗口。 每个像素与预定义的3D深度信息相关联并且还与匹配曲线相关联。 被摄体像素位于由窗口重叠的多个像素内。 计算与窗口重叠的多个像素相关联的平均3D深度信息，并且如果所计算的平均3D深度信息在与对象像素相关联的匹配曲线的误差区域内，则将计算出的平均3D深度信息分配给 主体像素的3D深度信息。 版权所有（C）2004，JPO
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19.发明专利Branch fetch architecture for reducing branch penalty without branch prediction 审中-公开用于减少分支预算的分支机构的分支机构架构
公开(公告)号：JP2003058366A
公开(公告)日：2003-02-28
申请号：JP2002219623
申请日：2002-07-29
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： KARIM FARAYDON O , CHANDRA RAMESH
CPC classification number: G06F9/3804 , G06F9/3842
Abstract: PROBLEM TO BE SOLVED: To provide new fetch branch architecture for reducing branch penalty without branch prediction.
SOLUTION: In lieu of the branch prediction, a merged fetch-branch unit operates in parallel with a decode unit in a processor. Upon detection of a branch instruction within a group of one or more fetched instructions, any instructions preceding the branch are marked as regular instructions, the branch instruction is marked as such and any instructions following the branch are marked as sequential instructions. Within two cycles, sequential instructions following the last fetched instruction are retrieved and marked, target instructions beginning at the branch target address are retrieved and marked and the branch is resolved. Either the sequential or target instructions are then dropped depending on the branch resolution, incurring a fixed, 1 cycle branch penalty.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供新的提取分支体系结构，以减少分支损失，无需分支预测。 解决方案：代替分支预测，合并的分支单元与处理器中的解码单元并行操作。 一旦检测到一个或多个获取的指令的组内的分支指令，分支之前的任何指令被标记为常规指令，则分支指令被标记为这样，并且分支之后的任何指令被标记为顺序指令。 在两个周期内，检索并标记最后取出的指令之后的顺序指令，检索并标记在分支目标地址处开始的目标指令，并解析分支。 然后根据分支分辨率，顺序或目标指令被丢弃，产生固定的1个循环分支罚分。
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20.发明专利Circuit and method for detecting servo wedge on spin-up of data-storage disk 审中-公开用于检测数据存储盘旋转时的伺服电路的电路和方法
公开(公告)号：JP2003051166A
公开(公告)日：2003-02-21
申请号：JP2002186323
申请日：2002-06-26
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： OZDEMIR HAKAN
CPC classification number: G11B5/59633 , G11B19/20 , G11B19/28
Abstract: PROBLEM TO BE SOLVED: To provide an improved servo circuit and a method for detecting a servo wedge on the spin-up of a data storage disk.
SOLUTION: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or after the disk attains an operating speed. By detecting a servo wedge instead of a spin-up wedge to determine an initial head position on disk spin up, such a servo circuit allows one to increase the disk's storage capacity by reducing the number of, or altogether eliminating, spin-up servo wedges from the disk.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种改进的伺服电路和用于在数据存储盘的旋转上检测伺服楔的方法。 解决方案：伺服电路包括伺服通道和处理器。 伺服通道从数据存储盘上识别相应数据扇区的伺服楔恢复伺服数据。 处理器检测到在盘旋转时的伺服楔形中的一个，即在盘达到或在盘达到操作速度之后。 通过检测伺服楔而不是旋转楔以确定磁盘上升的初始磁头位置，这样的伺服电路允许通过减少旋转伺服楔的数量或完全消除磁盘的存储容量来增加磁盘的存储容量 从磁盘。
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