公开(公告)号：WO2007069281A1

公开(公告)日：2007-06-21

申请号：PCT/IT2005/000732

申请日：2005-12-13

Applicant: STMICROELECTRONICS S.R.L. ,  SCOLLO, Rosario ,  NANIA, Massimo

Inventor： SCOLLO, Rosario ,  NANIA, Massimo

IPC: H03K17/0412 ,  H03K17/567

CPC classification number: H03K17/567 ,  H03K17/0412

Abstract: The invention relates to a driving circuit (30) for an emitter-switching configuration (21) of transistors (BJT, MOS) having at least one first and one second control terminal (X1, X2) connected to the driving circuit (30) to form a controlled emitter-switching device (35) having in turn respective collector, source and gate terminals (C, S, G). Advantageously the driving circuit (30) comprises at least one IGBT device (22) inserted between the collector terminal (C) and a first end of a capacitor (C1), whose second end is connected to the first control terminal (X1), the IGBT device (22) having in turn a third control terminal (X3) connected, through a first resistive element (R1), to the gate terminal (G), as well as a second resistive element (R2) inserted between the gate terminal (G) and the second control terminal (X2). Advantageously, the driving circuit (30) further comprises an additional supply (Va) inserted between the first and second ends of the capacitor (Cl) to ensure its correct biasing.

Abstract translation: 本发明涉及一种用于晶体管（BJT，MOS）的发射极 - 开关配置（21）的驱动电路（30），其具有至少一个连接到驱动电路（30）的第一和第二控制端（X1，X2），连接到驱动电路 形成受控的发射极开关器件（35），其又具有集电极，源极和栅极端子（C，S，G）。 有利地，驱动电路（30）包括插入在集电极端子（C）和第二端连接到第一控制端子（X1）的电容器（C1）的第一端之间的至少一个IGBT器件（22）， 具有通过第一电阻元件（R1）连接到栅极端子（G）的第三控制端子（X3）的IGBT器件（22）以及插入在栅极端子（R）之间的第二电阻元件（R2） G）和第二控制端子（X2）。 有利地，驱动电路（30）还包括插入在电容器（C1）的第一和第二端之间的附加电源（Va），以确保其正确的偏置。

公开(公告)号：WO2007042336A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006/064298

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02 ,  B81B7/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

公开(公告)号：WO2007006506A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006674

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10) comprising a superficial semiconductor layer (11), the method comprising the steps of: forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) carrying out at least a first ion implantation of a first type of dopant for forming at least one deep implanted region (14a); carrying out at least a second ion implantation of the first type of dopant for forming at least one body region (16) of the MOS transistor aligned with the deep implanted region (14a); the method comprising an activation thermal process with 1-14 low thermal budget of the first type and second type of dopant suitable to complete said formation of the body region (16), and of the deep implanted region (14a).

Abstract translation: 在宽带隙半导体衬底（10）上制造垂直功率MOS晶体管的方法，包括表面半导体层（11），所述方法包括以下步骤：在所述表面半导体层（11）上形成屏蔽结构（12），包括： 至少一个电介质层（12）至少执行用于形成至少一个深注入区域（14a）的第一类型掺杂剂的第一离子注入; 执行所述第一类型掺杂剂的至少第二离子注入以形成与所述深注入区域（14a）对准的所述MOS晶体管的至少一个体区（16）。 该方法包括具有适合于完成所述体区（16）的所述第一类型和第二类型掺杂物的1-14低热预算的激活热处理以及所述深注入区域（14a）。

公开(公告)号：WO2006117809A1

公开(公告)日：2006-11-09

申请号：PCT/IT2005/000258

申请日：2005-05-04

Applicant: STMICROELECTRONICS S.R.L. ,  GIUSSANI, Luca ,  SALATI, Luca

Inventor： GIUSSANI, Luca ,  SALATI, Luca

IPC: H05B41/298

CPC classification number: H05B41/2983

Abstract: The present invention refers to a driving device of a discharge lamp (10) having two cathodes. Said device comprises first means (1, 11) having a supply input voltage (Val) and suitable for providing an alternating voltage at the ends of the cathodes, second means (3) capable of monitoring a condition of each of said cathodes and suitable for measuring a first direct voltage signal (Vdc) of the waveform of the voltage of the lamp that develops when the lamp (10) approaches the ageing condition, third means (40) coupled to the second means (3) and suitable for deactivating the first means (11), fourth means (50) suitable for providing to the third means (40) a second direct voltage signal (Vdca) proportional in value to the supply voltage (Val). The third means (40) are suitable for deactivating the first means (11) when a predetermined variation of the first direct voltage signal (Vdc) occurs in relation to the second direct voltage signal (Vdca).

Abstract translation: 本发明涉及具有两个阴极的放电灯（10）的驱动装置。 所述装置包括具有电源输入电压（Val）并且适于在阴极端部提供交流电压的第一装置（1,11），能够监测每个阴极的状况并适合于 测量当灯（10）接近老化条件时产生的灯的电压的波形的第一直流电压信号（Vdc）;耦合到第二装置（3）并适于停用第一 装置（11），适于向第三装置（40）提供与电源电压（Val）成比例的第二直流电压信号（Vdca）的第四装置（50）。 当相对于第二直流电压信号（Vdca）发生第一直流电压信号（Vdc）的预定变化时，第三装置（40）适于停用第一装置（11）。

公开(公告)号：WO2006109329A1

公开(公告)日：2006-10-19

申请号：PCT/IT2005/000205

申请日：2005-04-12

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMBETTI, Osvaldo, Enrico ,  ZAFARANA, Alessandro

Inventor： ZAMBETTI, Osvaldo, Enrico ,  ZAFARANA, Alessandro

IPC: H02M3/156 ,  G05F1/565

CPC classification number: H02M3/1584 ,  H02M2001/0009

Abstract: The invention relates to a multiphase voltage regulator providing a voltage Vout to an output terminal (25) and of the type comprising N switches (3a 3b,..3n) located in parallel, providing respective current phases (Iphase1, iphase2,...IphaseN) added to each other to generate a total current (Iout) for a general load (Cout). The voltage regulator has N inductive circuits (5a 5b,..5n), each interposed between an output node (20a, 20b,..20n) of each of the N switches (3a 3b,...3n) and the output terminal (25), a sense circuit (8) which adds the voltages being in each of said output nodes (20a -20b,..20n) of said N switches (3a 3b,...3n) bringing the added voltage to an input of an amplifier circuit (10) having a second input (12) connected to the output terminal (25) to output a current (Ics) being proportional to said total current (Iout). The regulator also having a controller (15) with only two pins CS+ and CS- to read the total current (Iout), said two pins CS+ and CS- connected to the inputs of the amplifier (10).

Abstract translation: 本发明涉及向并联布置的N个开关（3a 3b，​​... 3n）的输出端（25）和包括N个开关（3a 3b，​​... 3n）的类型提供电压Vout的多相电压调节器，提供相应的电流相位（Iphase1，iphase2，...） IphaseN）相加，以产生一般负载（Cout）的总电流（Iout）。 电压调节器具有N个感应电路（5a 5b，... 5n），每个电感电路分别插入在N个开关（3a 3b，​​... 3n）中的每一个的输出节点（20a，20b，... 20n）和输出端子 （25），感测电路（8），其将所述N个开关（3a 3b，​​... 3n）的所述输出节点（20a-20b，... 20n）中的每一个中的电压相加， 具有连接到输出端子（25）的第二输入（12）的放大器电路（10），以输出与所述总电流（Iout）成比例的电流（Ics）。 调节器还具有仅具有两个引脚CS +和CS-的控制器（15）来读取总电流（Iout），所述两个引脚CS +和CS-连接到放大器（10）的输入。

公开(公告)号：WO2006045717A3

公开(公告)日：2006-05-04

申请号：PCT/EP2005/055338

申请日：2005-10-18

Applicant: STMICROELECTRONICS s.r.l. ,  D'ARRIGO, Angelo ,  MARINO, Filippo

Inventor： D'ARRIGO, Angelo ,  MARINO, Filippo

IPC: G05F1/10 ,  H02J7/00

Abstract: The present invention describes a device suitable for charging a 5 battery comprising at least a first (M10) and a second (M20) transistor. The transistors (M10, M20) are connected to an input voltage (Vin) and have output terminals; the output terminal of the first transistor (M10) is connected to the battery (LOAD). The device comprises a circuit (100) for driving the transistors (M10, M20) and said drive circuit (100) comprises 10 first means (CA1) suitable for regulating the current (Iout) in the battery during the charging phase of the battery (LOAD). The first means (CA1) are suitable for keeping the voltage on the output terminals of the transistors (M10, M20) the same during the charging phase of the battery (LOAD).

公开(公告)号：WO2005111758A1

公开(公告)日：2005-11-24

申请号：PCT/IT2004/000280

申请日：2004-05-18

Applicant: STMICROELECTRONICS S.R.L. ,  SCOLLO, Rosario ,  LEO, Santina

Inventor： SCOLLO, Rosario ,  LEO, Santina

IPC: G05F1/70

CPC classification number: H02M1/4225 ,  H05B41/28 ,  Y02B70/126

Abstract: A method for controlling the power factor of a power supply line is described, the method using a control cell connected to the power supply line. Advantageously according to the invention, the power factor control is performed by modulating the conduction time of a bipolar transistor (TB1) comprised in the control cell and by regulating this modulation of the conduction time by feedback-driving a control terminal (B1) of the bipolar transistor (TB1). A circuit for controlling the power factor of a power supply line is also described, of the type comprising a first and second input terminal (I1, I2) connected to the power supply line, as well as a first and second output terminal (O1, O2) connected to a load. Advantageously according to the invention, the control circuit comprises a power factor control cell (15) and a regulation block (16) feedback-connected thereto. The power factor control cell (15) comprising a bipolar transistor (TB1) inserted between the first and second input terminals (I1, I2) and having a control terminal (B1) connected to an output terminal (O4) of the regulation block (16), comprising in turn at least a supplementary transistor (Q2) having a conduction terminal connected to the output terminal (O4) to reduce the charges in the control terminal (B1) of the bipolar transistor (TB1).

Abstract translation: 描述了一种用于控制电源线的功率因数的方法，该方法使用连接到电源线的控制单元。 有利地，根据本发明，通过调制包含在控制单元中的双极晶体管（TB1）的导通时间并通过反馈驱动控制端子（B1）来调节该导通时间的调制来执行功率因数控制， 双极晶体管（TB1）。 还描述了用于控制电源线的功率因数的电路，其类型包括连接到电源线的第一和第二输入端子（I1，I2），以及第一和第二输出端子（O1， O2）连接到负载。 有利地，根据本发明，控制电路包括功率因数控制单元（15）和与其反馈连接的调节块（16）。 功率因数控制单元（15）包括插入在第一和第二输入端子（I1，I2）之间的双极晶体管（TB1），并具有连接到调节块（16）的输出端子（O4）的控制端子 ），至少包括具有连接到输出端子（O4）的导通端子的辅助晶体管（Q2），以减少双极晶体管（TB1）的控制端子（B1）中的电荷。

公开(公告)号：WO2005098806A1

公开(公告)日：2005-10-20

申请号：PCT/IT2004/000191

申请日：2004-04-08

Applicant: STMICROELECTRONICS S.R.L. ,  TOHOKU PIONEER CORPORATION ,  PULVIRENTI, Francesco ,  BONTEMPO, Gregorio ,  MASAKI, Murakata ,  AKINORI, Hayafuji

Inventor： PULVIRENTI, Francesco ,  BONTEMPO, Gregorio ,  MASAKI, Murakata ,  AKINORI, Hayafuji

IPC: G09G3/22

CPC classification number: G09G3/3216 ,  G09G3/22 ,  G09G3/3283 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/028

Abstract: An OLED (organic light-emitting diode) passive-matrix display (26) includes a display portion (10) and a driver portion (28). The display portion (10) includes a matrix of OLEDs (13) for displaying information. The driver portion (28) includes a monitor circuit (32) and a voltage adjusting circuit (34). The voltage adjusting circuit (34) has a power-up portion (36) that generates a supply voltage (VH) based on a reference voltage (VREF). In response to an indication to switch modes, the voltage adjusting circuit (34) switches to an operational mode wherein the supply voltage (VH) is generated based on the maximum voltage drop read across the OLEDs (13).

Abstract translation: OLED（有机发光二极管）无源矩阵显示器（26）包括显示部分（10）和驱动器部分（28）。 显示部分（10）包括用于显示信息的OLED（13）矩阵。 驱动器部分（28）包括监控电路（32）和电压调节电路（34）。 电压调节电路（34）具有基于参考电压（VREF）产生电源电压（VH）的上电部分（36）。 响应于切换模式的指示，电压调节电路（34）切换到操作模式，其中基于跨越OLED（13）读取的最大电压降产生电源电压（VH）。

公开(公告)号：WO2005086333A1

公开(公告)日：2005-09-15

申请号：PCT/EP2005/050737

申请日：2005-02-21

Applicant: STMICROELECTRONICS s.r.l. ,  ADRAGNA, Claudio ,  FAGNANI, Mauro

Inventor： ADRAGNA, Claudio ,  FAGNANI, Mauro

IPC: H02M3/28

CPC classification number: H02M3/28 ,  H02M2001/0006 ,  H02M2001/009

Abstract: The present invention refers to switching power supplies and in particular to a circuit for reducing the variations of auto-supply voltage of a control circuit of a switching power supply. In an embodiment thereof the circuit for reducing the variations of the auto-supply voltage (Vcc) of a control circuit (12) of a switching power supply where said control circuit (12) supplies an activation or deactivation signal of a power transistor comprises: a generator (Wa) of said auto-supply voltage (Vcc); characterized in that it comprises a controlled switch (T) capable of selectively connecting said generator (Wa) to said control circuit (12); and a driving circuit (SW2) of said controlled switch (T) that supplies a closing signal of said controlled switch (T) after a predefined delay of time (Td) starting from said deactivation command.

Abstract translation: 本发明涉及开关电源，特别是涉及用于减小开关电源的控制电路的自动供电电压的变化的电路。 在其实施例中，用于减小开关电源的控制电路（12）的变化的电路，其中所述控制电路（12）提供功率晶体管的激活或去激活信号包括： 所述自动电源电压（Vcc）的发电机（Wa）; 其特征在于，其包括能够选择性地将所述发电机（Wa）连接到所述控制电路（12）的受控开关（T）; 以及所述受控开关（T）的驱动电路（SW2），其在从所述去激活命令开始的预定的延迟时间（Td）之后提供所述受控开关（T）的闭合信号。

公开(公告)号：WO2005064911A1

公开(公告)日：2005-07-14

申请号：PCT/IB2004/004032

申请日：2004-12-06

Applicant: STMICROELECTRONICS S.R.L. ,  MASCHERA, Davide ,  DARIO, Daniele

Inventor： MASCHERA, Davide ,  DARIO, Daniele

IPC: H04M11/06

CPC classification number: H03H11/40 ,  H04L27/2601

Abstract: The arrangement includes a transformer (T) having a primary winding (L1) and a secondary winding (L2), the transformer exhibiting an impedance (Zsh) across the primary winding (2), and an impedance synthesis circuit (K, H(s),g). The impedance synthesis circuit includes a transfer function element (H(s)) having a frequency spectrum. The transfer function element (H(s)) has associated a gain element (K) and a current source (g) controlled by the transfer function element (H(s)). The impedance synthesis circuit (K, H(s),g) is connected to said secondary winding (L2), so that the transformer (T) mirrors the impedance synthesized by the impedance synthesis circuit (K, H(s),g) into the impedance (Zsh) across said primary winding (Li). The primary (Li) winding is adapted to define the high voltage (HV) side of an XDSL splitter, while the impedance synthesis circuit (K, H(s),g) connected to the secondary winding (L2) is inherently a low voltage circuit.

Abstract translation: 该装置包括具有初级绕组（L1）和次级绕组（L2）的变压器（T），变压器在初级绕组（2）两端呈现阻抗（Zsh），以及阻抗合成电路（K，H（s ），G）。 阻抗合成电路包括具有频谱的传递函数元素（H（s））。 传递函数元素（H（s））已经将增益元素（K）和由传递函数元素（H（s））控制的电流源（g）相关联。 阻抗合成电路（K，H（s），g）连接到所述次级绕组（L2），使得变压器（T）反映由阻抗合成电路（K，H（s），g）合成的阻抗， 穿过所述初级绕组（Li）的阻抗（Zsh）。 初级（Li）绕组适于限定XDSL分离器的高压（HV）侧，而连接到次级绕组（L2）的阻抗合成电路（K，H（s），g）固有地是低电压 电路。