公开(公告)号：WO2013148441A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/033159

申请日：2013-03-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ASARO, Anthony ,  NORMOYLE, Kevin ,  HUMMEL, Mark

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract translation: 一种用于将计算机装置中的处理器执行的存储器操作分配给存储器的方法和系统，所述计算机装置具有配置成与第二处理器统一操作的第一处理器 该方法包括从处理器接收存储器操作并将存储器操作映射到多个存储器堆中的一个。 映射生成映射结果。 该方法还包括向处理器提供映射结果。

公开(公告)号：WO2013085511A1

公开(公告)日：2013-06-13

申请号：PCT/US2011/063830

申请日：2011-12-07

Applicant: INTEL CORPORATION ,  VAN DE VEN, Adriaan

Inventor： VAN DE VEN, Adriaan

IPC: G06F9/44 ,  G06F12/08

CPC classification number: G06F12/0284 ,  G06F8/54 ,  G06F9/44521 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/151 ,  G06F2212/657 ,  Y02B70/16

Abstract: Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit coupled to the processor circuit to store private memory pages for multiple virtual machines, and a dynamic linker application operative on the processor circuit to link a binary version of a software program with associated program modules at run-time of the binary version on a virtual machine. The dynamic linker application may comprise a master prelink component operative on the processor circuit to relocate a first set of program modules for a first binary version of the software program for a first virtual machine using a first set of virtual memory addresses from a first private memory page allocated to the first virtual machine, and store relocation information for the first set of program modules in a global prelink layout map for use by a second virtual machine. Other embodiments are described and claimed.

Abstract translation: 描述了用于预先链接软件以改善虚拟系统中的重复数据删除的技术。 设备可以包括处理器电路，耦合到处理器电路以存储用于多个虚拟机的专用存储器页面的存储器单元以及在处理器电路上操作的动态链接器应用，以将软件程序的二进制版本与相关联的程序模块相链接 二进制版本在虚拟机上的运行时间。 动态链接器应用可以包括在处理器电路上操作的主预链接部件，用于使用来自第一专用存储器的第一组虚拟存储器地址，为第一虚拟机重新定位用于第一虚拟机的软件程序的第一二进制版本的第一组程序模块 页面，并且将第一组程序模块的重定位信息存储在全局预链接布局图中以供第二虚拟机使用。 描述和要求保护其他实施例。

公开(公告)号：WO2013032437A1

公开(公告)日：2013-03-07

申请号：PCT/US2011/049584

申请日：2011-08-29

Applicant: INTEL CORPORATION ,  KACEVAS, Nicolas

Inventor： KACEVAS, Nicolas

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/1045 ,  G06F12/1036

Abstract: Agents may be assigned to discrete portions of a cache. In some cases, more than one agent may be assigned to the same cache portion. The size of the portion, the assignment of agents to the portion and the number of agents may be programmed dynamically in some embodiments.

Abstract translation: 代理可以被分配到高速缓存的离散部分。 在某些情况下，可以将多个代理分配给相同的高速缓存部分。 在一些实施例中，部分的大小，代理对部分的分配和代理的数量可以被动态地编程。

公开(公告)号：WO2012058371A3

公开(公告)日：2012-07-19

申请号：PCT/US2011057994

申请日：2011-10-27

Applicant: UNISYS CORP

Inventor： KERSHNER DAVID A

IPC: G06F12/00 ,  G06F9/44 ,  G06F12/08

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1081 ,  G06F12/109 ,  G06F2009/45579 ,  G06F2212/151

Abstract: A soft partitioning system for allowing multiple virtual system environments to execute on a single platform may include I/O service partitions (IOSPs). The IOSPs operating in a separate virtual memory space on the platform and service disk and network requests from multiple guests. The IOSPs provide translation from virtual addresses to physical addresses such that from the point of view of the guest the virtual addresses used by the guest appear to be physical addresses. The IOSP may be implemented in a Linux kernel. The address space of the IOSP may be extended to include DMA memory sections such that the Linux kernel does not include all of the guest's memory. The IOSP may operate on hardware that does or does not support virtualization technology for directed I/O,

Abstract translation: 用于允许多个虚拟系统环境在单个平台上执行的软分区系统可以包括I / O服务分区（IOSP）。 IOSP在平台上独立的虚拟内存空间中运行，服务磁盘和多个来宾的网络请求。 IOSP提供从虚拟地址到物理地址的转换，使得从guest虚拟机的角度来看guest虚拟机使用的虚拟地址看起来是物理地址。 IOSP可以在Linux内核中实现。 IOSP的地址空间可以扩展到包含DMA内存部分，以便Linux内核不包含所有客户的内存。 IOSP可以在支持或不支持针对定向I / O的虚拟化技术的硬件上运行，

公开(公告)号：WO2012025793A1

公开(公告)日：2012-03-01

申请号：PCT/IB2010/053852

申请日：2010-08-26

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  LEVENGLICK, Dov

Inventor： LEVENGLICK, Dov

IPC: G06F12/06 ,  G06F9/46

CPC classification number: G06F12/145 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/1491 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/657

Abstract: The invention pertains to a memory management unit (20) for a microprocessor system (10), the memory management unit (20) being connected or connectable to at least one processor core (12) of the microprocessor system (10) and being connected or connectable to a physical memory (14) of the microprocessor system (10). The memory management unit (20) is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit (20) comprises a first register table (22) indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table (24) indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit (20) is adapted to prevent write access to the second register table (24) by a process not in hypervisor mode. The memory management unit (20) is further adapted to allow write access to the first register table (22) of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table (22) with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table (22) of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system (12) and a method for managing memory.

Abstract translation: 本发明涉及一种用于微处理器系统（10）的存储器管理单元（20），该存储器管理单元（20）被连接或连接到该微处理器系统（10）的至少一个处理器核心（12）并被连接或 可连接到微处理器系统（10）的物理存储器（14）。 存储器管理单元（20）适于在管理程序模式或管理程序模式下选择性地操作，管理程序模式和管理程序模式具有不同的访问硬件的特权级别。存储器管理单元（20）包括第一寄存器表 指示用于将至少一个逻辑物理地址和至少一个实际物理地址映射到彼此的物理地址信息; 第二寄存器表（24），其指示在主管模式中或在管理程序模式下运行的进程可访问的物理地址的允许地址范围; 其中所述存储器管理单元（20）适于通过不处于管理程序模式的进程来防止对所述第二寄存器表（24）的写入访问。 存储器管理单元（20）还适于允许对在第一寄存器表（22）中指示的或在管理程序模式下运行的进程的第一寄存器表（22）进行写访问，以用存储器映射信息重新配置在第一寄存器表（22）中指示的物理地址信息 涉及至少一个物理地址，如果所述至少一个物理地址在所述允许的地址范围内，并且为了防止在所述至少一个物理地址范围内或在管理员模式下运行的进程的第一登记表（22）的写入访问 地址不在允许的地址范围内。 本发明还涉及一种微处理器系统（12）和一种用于管理存储器的方法。

公开(公告)号：WO2011011769A1

公开(公告)日：2011-01-27

申请号：PCT/US2010/043169

申请日：2010-07-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  KEGEL, Andrew, G. ,  HUMMEL, Mark, D.

Inventor： KEGEL, Andrew, G. ,  HUMMEL, Mark, D.

IPC: G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/151

Abstract: An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables

Abstract translation: 被配置为将I / O设备对I / O设备的请求控制到系统存储器的输入/输出存储器管理单元（IOMMU）包括控制逻辑，其可以执行两级客户转换以转换与I / O设备生成的请求相关联的地址 使用存储在系统存储器中的翻译数据。 翻译数据包括具有多个条目的设备表。 控制逻辑可以通过使用与产生请求的I / O设备相对应的设备标识符来为给定请求选择设备表条目。 翻译数据还可以包括第一组I / O页表，其包括一组访客页表和一组嵌套页表。 用于给定请求的所选择的设备表条目可以包括指向一组客户转换表的指针，并且最后的客户转换表包括指向该嵌套页表集合的指针

公开(公告)号：WO2010144216A2

公开(公告)日：2010-12-16

申请号：PCT/US2010/035101

申请日：2010-05-17

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MOYER, William, C. ,  EIFERT, James, B.

Inventor： MOYER, William, C. ,  EIFERT, James, B.

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/109

Abstract: Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor (12). For example, in some embodiments, a memory management unit (16) is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table (9). For a subset of less than all processes, entry selection logic (81) selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

Abstract translation: 已经开发了非侵入式技术来动态地和选择性地改变由处理器（12）执行的或对于处理器（12）执行的地址转换。 例如，在一些实施例中，存储器管理单元（16）被配置为将相应有效（或虚拟）地址空间中的有效地址映射到存储器中的物理地址，其中存储器管理单元执行的映射基于地址 地址转换表（9）的翻译条目。 对于少于所有进程的子集，条目选择逻辑（81）从在各个地址转换条目中编码的多个备选映射中进行选择。 对于为子集的特定过程映射的至少一些有效地址，特定地址转换条目的选择基于外部来源的值。 在一些实施例中，仅针对特定进程映射的有效地址的子集经受地址转换条目选择的动态运行时间更改。

公开(公告)号：WO2010135430A1

公开(公告)日：2010-11-25

申请号：PCT/US2010/035409

申请日：2010-05-19

Applicant: VMWARE, INC. ,  AHMAD, Irfan ,  WALDSPURGER, Carl, A.

Inventor： AHMAD, Irfan ,  WALDSPURGER, Carl, A.

IPC: G06F12/10

CPC classification number: G06F12/1018 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/152 ,  G06F2212/656

Abstract: Read requests to a commonly accessed storage volume are conditionally issued, depending on whether or not a requested data block is already stored in memory from a prior access or to be stored in memory upon completion of a pending request. A data structure is maintained in memory to track physical memory pages and to indicate for each physical memory page the corresponding location in the storage volume from which the contents of the physical memory were read and the number of virtual memory pages that are mapped thereto.

Abstract translation: 根据所请求的数据块是否已经从先前的访问中存储在存储器中，或者在完成未决请求时被存储在存储器中，有条件地发出对常用访问存储卷的读取请求。 在存储器中维护数据结构以跟踪物理存储器页面，并且为每个物理存储器页面指示从其读取物理存储器的内容的存储卷中的对应位置和映射到其的虚拟存储器页面的数量。

公开(公告)号：WO2009087133A1

公开(公告)日：2009-07-16

申请号：PCT/EP2009/050050

申请日：2009-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GREINER, Dan ,  GAINEY, Charles Jr. ,  HELLER, Lisa ,  OSISEK, Damian ,  PFEFFER, Erwin ,  SLEGEL, Timothy ,  WEBB, Charles

Inventor： GREINER, Dan ,  GAINEY, Charles Jr. ,  HELLER, Lisa ,  OSISEK, Damian ,  PFEFFER, Erwin ,  SLEGEL, Timothy ,  WEBB, Charles

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.

Abstract translation: 提供了增强的动态地址翻译工具。 在一个实施例中，首先获得待翻译的虚拟地址，并获得翻译表层次的翻译表的初始起始地址。 基于获得的初始来源，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用了格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段 - 帧绝对地址。 只有当访问控制字段与正在执行的程序状态字或操作数中的任何一个提供的程序访问键相匹配时，才允许存储操作。 如果与虚拟地址关联的程序访问密钥等于段访问控制字段，则允许提取操作。

公开(公告)号：WO2008036390A1

公开(公告)日：2008-03-27

申请号：PCT/US2007/020455

申请日：2007-09-21

Applicant: INTEL CORPORATION ,  ILLIKKAL, Rameshkumar, G. ,  NEWELL, Donald, K. ,  IYER, Ravishankar ,  MAKINENI, Srihari

Inventor： ILLIKKAL, Rameshkumar, G. ,  NEWELL, Donald, K. ,  IYER, Ravishankar ,  MAKINENI, Srihari

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/109 ,  G06F2212/656

Abstract: Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.

Abstract translation: 公开了在虚拟机环境中在客人之间共享信息的装置，方法和系统的实施例。 在一个实施例中，装置包括虚拟机控制逻辑，执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。