公开(公告)号：US20010023423A1

公开(公告)日：2001-09-20

申请号：US09805265

申请日：2001-03-13

Applicant: STMicroelectronics S.A.

Inventor： Fabrice Marinet

IPC: G06F001/02

CPC classification number: H03K3/84

Abstract: A pseudo-random number generator includes a first generator for producing a sawtooth waveform signal having a first frequency, and a second generator for producing a pulse signal having a second frequency. A sampling circuit samples the sawtooth waveform signal and the pulse signal for generating a sample signal of the sawtooth waveform signal at the second frequency. A coding circuit codes the amplitude of the sample signal to supply binary values. The pseudo-random number generator has applications in integrated circuits which are used in contact type or contactless IC cards.

Abstract translation: 伪随机数发生器包括用于产生具有第一频率的锯齿波形信号的第一发生器和用于产生具有第二频率的脉冲信号的第二发生器。 采样电路对锯齿波形信号和脉冲信号进行采样，以产生第二频率的锯齿波形信号的采样信号。 编码电路对采样信号的幅度进行编码以提供二进制值。 伪随机数发生器在用于接触型或非接触式IC卡的集成电路中具有应用。

公开(公告)号：US20010021117A1

公开(公告)日：2001-09-13

申请号：US09795657

申请日：2001-02-28

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink

IPC: G11C019/08

CPC classification number: G11C8/00 ,  G11C7/10 ,  G11C7/103 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/30

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract translation: 串行输入/输出存储器能够在接收到缺少形成完整地址的N个最低有效位的部分读取地址时读取存储器中的数据。 预读步骤包括：同时读取具有相同部分地址的存储器的M个字的P个第一位; 当接收到的地址完成时，选择由完整地址指定的字的P个第一位，并将这些位传送到存储器的串行输出; 在传送P个以前的位期间读取由完整地址指定的字的P后续位，并且当P个先前的位被递送时，将这些位递送到存储器的串行输出。

公开(公告)号：US20010015661A1

公开(公告)日：2001-08-23

申请号：US09727299

申请日：2000-11-30

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G05F001/56 ,  G05F001/618

CPC classification number: G05F3/247 ,  G01R19/16519 ,  G11C5/147

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

Abstract translation: 用于检测向集成电路的内部节点施加高电压信号的装置包括高压分压器电路和阈值检测电路。 阈值检测电路接收由分频电路的输出给出的信号，并且基于信号穿过阈值在其输出端提供阈值交叉检测信号。 检测电路连接在逻辑电源电压和地之间，并且还包括负反馈回路。 负反馈回路连接到除法器电路的输出端，以在检测阈值与信号交叉之后限制其输出处的高电压信号的电压积分。

公开(公告)号：US20010003540A1

公开(公告)日：2001-06-14

申请号：US09727300

申请日：2000-11-30

Applicant: STMicroelectronics S.A.

Inventor： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC: H04L009/12 ,  H04L009/16 ,  H04L012/22

CPC classification number: H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract translation: 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。

公开(公告)号：US20190372539A1

公开(公告)日：2019-12-05

申请号：US16428413

申请日：2019-05-31

Applicant: STMicroelectronics S.A.

Inventor： Renald Boulestin

IPC: H03G3/30 ,  H03F3/19 ,  H03K5/24 ,  H04B1/06

Abstract: A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.

公开(公告)号：US20170317658A1

公开(公告)日：2017-11-02

申请号：US15653014

申请日：2017-07-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A.

Inventor： Frédéric Gianesello ,  Romain Pilard ,  Cédric Durand

IPC: H03H7/42 ,  H01F27/40 ,  H01F27/29 ,  H01L23/522 ,  H01F27/38 ,  H04W88/02 ,  H01F27/28

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US20170026052A1

公开(公告)日：2017-01-26

申请号：US15039184

申请日：2014-11-21

Applicant: STMicroelectronics S.A.

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault ,  Rakhel Kumar Parida

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/0617 ,  H03M1/0614 ,  H03M1/0626 ,  H03M1/1215 ,  H03M1/1245

Abstract: A device can be used for compensating bandwith mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.

Abstract translation: 一种器件可用于补偿时间交错模数转换器的带宽不匹配。 该装置的处理器针对每个原始采样流确定表示相应转换器的低通滤波器的时间常数与参考低通滤波器的基准时间常数之间的估计差，并且使用该估计的差分和滤波后的 流以校正原始流并传送校正样本的校正流。

公开(公告)号：US09401351B2

公开(公告)日：2016-07-26

申请号：US14610173

申请日：2015-01-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract translation: 电子器件包括具有阳极，阴极，设置在阳极侧的第一双极晶体管的晶闸管。 第二双极晶体管设置在阴极侧。 这两个双极晶体管被嵌套并连接在阳极和阴极之间。 MOS晶体管耦合在第二双极晶体管的集电极区域和发射极区域之间。 晶体管具有通过并入第二双极晶体管的基极区的至少一部分的电阻半导体区连接到阴极的栅极区。

公开(公告)号：US09391015B2

公开(公告)日：2016-07-12

申请号：US14079393

申请日：2013-11-13

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Simon Jeannot ,  Pascal Tannhof

IPC: H01L21/02 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

公开(公告)号：US09362380B2

公开(公告)日：2016-06-07

申请号：US14104993

申请日：2013-12-12

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/737 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, =; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷， 以及通过在凹部中选择性地外延生长包含SiGe的膜来形成异质结双极晶体管的基极。