公开(公告)号：US5764110A

公开(公告)日：1998-06-09

申请号：US769801

申请日：1996-12-20

Applicant: Atsuhiko Ishibashi

Inventor： Atsuhiko Ishibashi

IPC: H03B1/00 ,  H03K3/011 ,  H03K3/03 ,  H03K3/354 ,  H03L1/00 ,  H03B5/04

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03K3/354 ,  H03L1/00 ,  H03B2201/02

Abstract: A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.

公开(公告)号：US5635878A

公开(公告)日：1997-06-03

申请号：US546406

申请日：1995-10-20

Applicant: Ding-Jen Liu ,  Ying-Tzung Wang

Inventor： Ding-Jen Liu ,  Ying-Tzung Wang

IPC: H03B1/00 ,  H03B1/04 ,  H03B5/24 ,  H03K3/0231 ,  H03L7/099

CPC classification number: H03B5/24 ,  H03K3/0231 ,  H03B2201/02 ,  H03B2202/042

Abstract: A differential-type voltage-controlled oscillator (VCO) with low-frequency stability compensation is disclosed. The differential-type VCO comprises a voltage-to-current converter for converting an input voltage signal into a biasing current signal to control the frequency of the VCO output. The VCO further comprises a number of stages of differential amplifiers connected in cascade. Each of the stages of differential amplifiers includes a pair of differential input PMOS transistors, with each of the PMOS transistors connected to a pair of NMOS load transistors. Each of the pair of NMOS load transistors are connected in parallel. The VCO further comprises a number of stages of bias circuits connected in cascade. Each of the bias circuits is connected to a corresponding stage of the differential amplifiers for receiving the bias current generated by the voltage-to-current converter. Each of the stages of bias circuits comprises a current source for supplying a constant current to maintain the low-frequency voltage-frequency linearity of the output of the VCO, and a biasing PMOS transistor connected in parallel with said current source.

Abstract translation: 公开了一种具有低频稳定性补偿的差分型压控振荡器（VCO）。 差分型VCO包括电压 - 电流转换器，用于将输入电压信号转换成偏置电流信号以控制VCO输出的频率。 VCO还包括级联连接的多级差分放大器。 差分放大器的每个级包括一对差分输入PMOS晶体管，每个PMOS晶体管连接到一对NMOS负载晶体管。 一对NMOS负载晶体管中的每一个并联连接。 VCO还包括级联连接的多级偏置电路。 每个偏置电路连接到差分放大器的相应级，用于接收由电压 - 电流转换器产生的偏置电流。 偏置电路的每个级包括用于提供恒定电流以维持VCO的输出的低频电压 - 频率线性度的电流源和与所述电流源并联连接的偏置PMOS晶体管。

公开(公告)号：US5581216A

公开(公告)日：1996-12-03

申请号：US377269

申请日：1995-01-24

Applicant: John E. Ruetz

Inventor： John E. Ruetz

IPC: H03B1/00 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/354 ,  H03B5/24 ,  H03L7/099

CPC classification number: H03K3/0231 ,  H03K3/013 ,  H03K3/354 ,  H03B2201/02

Abstract: A voltage controlled oscillator circuit includes a predetermined number of interconnected differential comparator cells having source connected p-channel and n-channel transistors, a biasing transistor connected to the sources of the p-channel or n-channel transistors, and clamping circuits connected to said first and second n-channel transistors. The voltage controlled oscillator circuit further includes filter circuitry for filtering the input currents to the biasing transistor.

Abstract translation: 压控振荡器电路包括具有源极连接的p沟道和n沟道晶体管的预定数量的互连的差分比较器单元，连接到p沟道或n沟道晶体管的源极的偏置晶体管，以及连接到所述 第一和第二n沟道晶体管。 压控振荡器电路还包括用于滤波到偏置晶体管的输入电流的滤波器电路。

公开(公告)号：US5574406A

公开(公告)日：1996-11-12

申请号：US525689

申请日：1995-09-28

Applicant: Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

Inventor： Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

IPC: H03B1/00 ,  H03L7/099 ,  H03L7/113 ,  H03L7/14 ,  H04N7/12

CPC classification number: H03L7/14 ,  H03L7/0991 ,  H03L7/113 ,  H04N7/122 ,  H03B2201/02 ,  H03B2201/0266 ,  H03J2200/10

Abstract: In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.

Abstract translation: PCT No.PCT / US94 / 04307 Sec。 371 1995年9月28日第 102（e）1995年9月28日PCT PCT 1994年4月19日PCT公布。 公开号WO94 / 24769 日期1994年10月27日在锁相环电路中，频率检测器测量在交替的水平行周期中的振荡信号和同步信号之间的频率误差，以产生频率误差指示信号。 频率误差指示信号被施加到用于校正其它交替水平行周期中的频率误差的振荡器，以防止频率误差测量和校正发生在相同的水平行周期中。

公开(公告)号：US5528124A

公开(公告)日：1996-06-18

申请号：US408904

申请日：1995-03-22

Applicant: Kunihiko Azuma

Inventor： Kunihiko Azuma

IPC: H04N9/64 ,  H03B1/00 ,  H03C3/00 ,  H03C3/04 ,  H03H11/20 ,  G05F1/00

CPC classification number: H03H11/20 ,  H03B2201/02 ,  H03C3/04

Abstract: A phase control circuit for operating a phase shift in accordance with a control voltage comprises four differential circuits, two of which form a multiplier circuit for providing a basic function for a phase shift operation of the phase control circuit, and the rest of which cancel variations in amplitude generated during the phase shift operation. The amplitude compensation is accomplished by a construction in which a ratio of an emitter area of a first bipolar transistor in each of the differential circuits to an emitter area of the second bipolar transistor in each of the differential circuits is set at a value between 2 and 3. Alternatively, the amplitude compensation is provided by a level shift circuit providing an offset voltage in the control voltage supplied to two of the differential circuits.

Abstract translation: 用于根据控制电压进行相移的相位控制电路包括四个差分电路，其中两个形成用于提供相位控制电路的相移操作的基本功能的乘法器电路，其余的差分电路取消变化 在相移操作期间产生的振幅。 幅度补偿通过以下结构来实现，其中每个差分电路中的每个差分电路中的第一双极晶体管的发射极面积与每个差分电路中的第二双极晶体管的发射极区域的比率被设定在2和 或者，幅度补偿由提供给两个差分电路的控制电压中的偏移电压的电平移位电路提供。

公开(公告)号：US5418497A

公开(公告)日：1995-05-23

申请号：US270624

申请日：1994-07-05

Applicant: Frederick L. Martin

Inventor： Frederick L. Martin

IPC: H03B1/00 ,  H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1209 ,  H03B5/1225 ,  H03B5/1243 ,  H03B5/1296 ,  H03B2200/0062 ,  H03B2201/02 ,  H03B2201/0275

Abstract: BiCMOS technology is used in the design of a VCO (200) to improve low DC operation. The VCO (200) includes two coupled oscillator circuits (201,219) tuned to different fixed frequencies such that the oscillator resonant frequencies define the tuning range of the VCO (200). The oscillator circuits (201, 219) are coupled such that the frequency of oscillation of the VCO (200) is adjustable via variable resistors (206, 214) by manipulating the bias currents to the two oscillator circuits (201,219). A biasing circuit (208) along with variable resistors (206 and 214) provide the DC bias to the oscillator circuits (201 and 219). The biasing circuit (208) maintains the sum of the biasing currents to the oscillator circuits constant. The oscillator circuits (201, and 219) are interconnected utilizing an RF coupling circuit (211). The VCO (200) is capable of operating at voltages as low as 1.8 volts DC.

Abstract translation: BiCMOS技术用于VCO（200）的设计，以改善低直流操作。 VCO（200）包括调谐到不同固定频率的两个耦合振荡器电路（201,219），使得振荡器谐振频率定义VCO（200）的调谐范围。 振荡器电路（201,219）被耦合，使得VCO（200）的振荡频率可通过可变电阻器（206,214）调节到两个振荡器电路（201,219）的偏置电流来调节。 偏置电路（208）连同可变电阻器（206和214）将DC偏压提供给振荡器电路（201和219）。 偏置电路（208）将偏置电流的和保持恒定。 振荡器电路（201和219）利用RF耦合电路（211）互连。 VCO（200）能够在低至1.8伏DC的电压下工作。

公开(公告)号：US5343170A

公开(公告)日：1994-08-30

申请号：US2266

申请日：1993-01-08

Applicant: Junseong Lee

Inventor： Junseong Lee

IPC: H03B7/00 ,  H03B1/00 ,  H03B1/04 ,  H03B5/00 ,  H03B5/20 ,  H03B5/24 ,  H03B7/06 ,  H03B27/00 ,  H03H11/46 ,  H03H11/52 ,  H03L7/099 ,  H03H11/00

CPC classification number: H03H11/46 ,  H03B5/24 ,  H03B7/06 ,  H03H11/52 ,  H03B1/04 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0092 ,  H03B2201/02 ,  H03B27/00 ,  H03B5/20

Abstract: A voltage controlled oscillator (VCO) including a negative feedback circuit operates in response to a negative feedback signal generated during active transistor region operation of transistors in transconductance amplifying stages coupled thereto. As a result, harmonic distortion and problems of noise and unstable frequency oscillation are obviated or significantly reduced. The VCO includes first and second variable transconductance (gm) amplifying stages whose non-inverting (+) and inverting (-) terminals are respectively grounded and a first condenser connected between an output terminal of the first transconductance (gm) amplifying stage and a non-inverting (+) terminal of the second transconductance (gm) amplifying stage. A negative-resistive circuit is used to provide a negative feedback.

Abstract translation: 包括负反馈电路的压控振荡器（VCO）响应于在与其耦合的跨导放大级中的晶体管的有源晶体管区域操作期间产生的负反馈信号而工作。 结果，谐波失真和噪声问题以及不稳定的频率振荡被消除或显着减少。 VCO包括第一和第二可变跨导（gm）放大级，其非反相（+）和反相（ - ）端分别接地，并且第一电容器连接在第一跨导（gm）放大级的输出端和非反相 - 第二跨导（gm）放大级的（+）端子。 负电阻电路用于提供负反馈。

公开(公告)号：US5300898A

公开(公告)日：1994-04-05

申请号：US921157

申请日：1992-07-29

Applicant: Dao-Long Chen ,  Robert D. Waldron

Inventor： Dao-Long Chen ,  Robert D. Waldron

IPC: H03B5/12 ,  H03B1/00 ,  H03K3/012 ,  H03K3/03 ,  H03K19/017 ,  H03B5/02 ,  H03B5/24

CPC classification number: H03K3/012 ,  H03K19/01721 ,  H03K3/0315 ,  H03B2201/02

Abstract: A differential inverter such as may be used in an oscillator circuit. The differential inverter is connected between first and second current sources. The differential inverter includes first and second single signal CMOS inverters connected in parallel between the first and second controlled current sources. Each of the current sources is a MOS transistor. A bias circuit is connected to the control gates of the MOS transistors and provides bias signals thereto, the bias circuit includes a variable current source with bias signals being generated in response to the current flow in the variable current source.

Abstract translation: 差分逆变器例如可以用在振荡器电路中。 差分逆变器连接在第一和第二电流源之间。 差分逆变器包括在第一和第二受控电流源之间并联连接的第一和第二单信号CMOS反相器。 每个电流源都是MOS晶体管。 偏置电路连接到MOS晶体管的控制栅极并向其提供偏置信号，偏置电路包括具有响应于可变电流源中的电流产生偏置信号的可变电流源。

公开(公告)号：US5185581A

公开(公告)日：1993-02-09

申请号：US858269

申请日：1992-03-26

Applicant: Anthony K. D. Brown

Inventor： Anthony K. D. Brown

IPC: H03B1/00 ,  H03B5/20 ,  H03B27/00

CPC classification number: H03B5/20 ,  H03B2200/0062 ,  H03B2201/02 ,  H03B27/00

Abstract: A differential amplifier includes a bias current source and a current dividing circuit for controllably dividing a bias current between first and second current paths. A first pair of matched transistors is connected as a differential pair between matched load impedances and the first current path. A second pair of matched transistors is connected as a differential pair between the matched load impedances and the second current path. Differential inputs of the second differential pair are connected to corresponding differential inputs of the second differential pair. The transistors of the first and second pairs have different emitter areas. Matched capacitors may be connected between respective differential inputs and differential outputs of the differential amplifier. The load impedances may be tapped to provide outputs having a lower differential gain. The differential amplifier is useful for building resonant circuits, for example voltage controlled oscillators having high Q factors.

Abstract translation: 差分放大器包括偏置电流源和用于可控地划分第一和第二电流路径之间的偏置电流的电流分配电路。 第一对匹配晶体管作为匹配的负载阻抗和第一电流路径之间的差分对连接。 第二对匹配晶体管作为匹配负载阻抗和第二电流路径之间的差分对连接。 第二差分对的差分输入连接到第二差分对的相应的差分输入。 第一对和第二对的晶体管具有不同的发射极区域。 匹配的电容器可以连接在差分放大器的差分输入和差分输出之间。 负载阻抗可以被抽头以提供具有较低差分增益的输出。 差分放大器可用于构建谐振电路，例如具有高Q因子的压控振荡器。

公开(公告)号：US5093634A

公开(公告)日：1992-03-03

申请号：US607019

申请日：1990-10-31

Applicant: John M. Khoury

Inventor： John M. Khoury

IPC: H03B1/00 ,  H03B5/20 ,  H03B27/00 ,  H03F1/56 ,  H03F3/345

CPC classification number: H03B5/20 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2200/0092 ,  H03B2201/02 ,  H03B27/00

Abstract: A clamped linear transconductance amplifier path, consisting essentially of a current clamp merged in a linear transconductance amplifier path, is used in a triple-input, triple-output transconductor (200). In a balanced transconductor in CMOS technology, this clamped linear transconductance amplifier path is formed by a p-channel MOS transistor (M23) separately connected in series with each of a matched pair of p-channel MOS transistors (M21,M22). The clamped linear transconductance amplifier path, together with two other transconductance paths (M15-M20; M9-M14), can be interconnected to form the input side of the triple-input, triple-output transconductor (200). By summing and integrating the outputs of the input side of the triple-input transconductor (200), the output (V.sub.OUT,P and V.sub.OUT,N) of the output side of the transconductor can be formed. By feeding back this output to the input side of the transconductor (200), an oscillator can be obtained.