公开(公告)号：PH12021551164A1

公开(公告)日：2021-10-25

申请号：PH12021551164

申请日：2021-05-21

Applicant: MICROSOFT TECHNOLOGY LICENSING LLC

Inventor： BAK YEVGENIY ,  IYIGUN MEHMET ,  KISHAN ARUN U

IPC: G06F12/02 ,  G06F9/50 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/126

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

公开(公告)号：GB2580968B

公开(公告)日：2021-08-04

申请号：GB201901436

申请日：2019-02-01

Applicant: ADVANCED RISC MACH LTD

Inventor： SIMON JOHN CRASKE ,  JACOB EAPEN

IPC: G06F12/14 ,  G06F12/1036 ,  G06F21/78

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

公开(公告)号：IL283228D0

公开(公告)日：2021-07-29

申请号：IL28322821

申请日：2021-05-18

Applicant: MICROSOFT TECHNOLOGY LICENSING LLC

IPC: G06F9/455 ,  G06F9/50 ,  G06F12/02 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/126

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

公开(公告)号：DE112018007268T5

公开(公告)日：2020-11-26

申请号：DE112018007268

申请日：2018-03-12

Applicant: INTEL CORP

Inventor： ZHOU YU ,  NIU BING

IPC: G06F12/1036

Abstract: Bei einem Beispiel ist eine Rechenvorrichtung offenbart, umfassend: eine Hardware-Plattform; einen Virtuelle-Maschine-Manager (VMM), der eine Virtuelle-Maschine-Steuerstruktur (VMCS) umfasst, wobei der VMM ausgebildet ist, um eine virtuelle Maschine (VM) gemäß der VMCS bereitzustellen; eine Datenstruktur, die eine erweiterte Seitentabelle (EPT) für die VM, die einen Übersetzungs-Lookaside-Puffer (TLB) aufweist, umfasst, wobei der TLB eine Region umfasst, die eine Durchgangsregion aufweist, die eine direkte virtuelle Gastadresse (GVA) zu der physischen Host-Adresse (HPA) -Übersetzungen umfasst; und Logik, um die Durchgangsregion zu sperren, um zu verhindern, dass die Durchgangsregion aus dem TLB ausgeschlossen wird.

公开(公告)号：GB2579614A

公开(公告)日：2020-07-01

申请号：GB201819922

申请日：2018-12-06

Applicant: TRUSTONIC LTD

Inventor： OLIVIER DEPREZ ,  LUKAS HÄNEL

IPC: G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14

Abstract: A page table isolation method comprising selecting, using a first pointer, a shadow kernel page table which itself references a shadow page 510, mapping the shadow page in a virtual address space and associating the shadow page with a global indicator. Selecting, using a second pointer, a first application page table from a number of such tables, the table being associated with a first address space identifier and referencing one or more application pages 540, 550 and mapping the application pages in the virtual address space and associating them with the address space identifier. Responsive to a request to transition from user to kernel mode, the first pointer may be changed to point towards a kernel page table referencing both the shadow kernel page and one or more kernel pages, and mapping the kernel pages in the virtual address space with a unique kernel address space identifier. When transitioning from kernel to user mode, the first pointer may be pointed back to the shadow kernel page table and the kernel pages may be unmapped from the virtual address space. The shadow kernel page may be trampoline code which manages the transition between user and kernel mode. An iteration on KAISER.

公开(公告)号：GB2570665A

公开(公告)日：2019-08-07

申请号：GB201801598

申请日：2018-01-31

Applicant: ADVANCED RISC MACH LTD

Inventor： GRAEME PETER BARNES ,  CATALIN THEODOR MARINAS

IPC: G06F12/1036 ,  G06F12/109 ,  G06F12/14

Abstract: An apparatus comprises address translation circuitry to perform a translation of a virtual address comprising a virtual tag portion and a virtual address portion into a physical address comprising a physical tag portion and a physical address portion. The address translation circuitry comprises address tag translation circuitry to perform a translation of the virtual tag portion into the physical tag portion. The address translation to be performed is selected in dependence on the virtual address, for example on the most significant bit of the virtual address portion. That bit might indicate whether the virtual address has been allocated to kernel-owned processes or to user-owned processes, and accordingly the physical tag portion either matches the virtual tag portion or is modified by the tag translation circuitry by being inverted or incremented. A predetermined part of the physical tag portion can trigger a guard tag comparison between the physical tag portion and a guard tag value associated with the memory location, and a mismatch may indicate a fault condition. A predetermined part of the physical tag portion may indicate a match-all or match-one comparison.

公开(公告)号：GB2550859A

公开(公告)日：2017-12-06

申请号：GB201609276

申请日：2016-05-26

Applicant: ADVANCED RISC MACH LTD

Inventor： GUILLAUME BOLBENES ,  JEAN-PAUL PONCELET

IPC: G06F12/1036 ,  G06F12/1009

Abstract: This application is related to correcting a mismatch between permissions of memory addresses during a two stage translation process. Specifically, if a memory management unit (MMU) 22 is required to perform a page table walk 26 as a result of a miss in the translation look-aside buffer 24, then a guest operating system will perform the first stage of the address translation and a hypervisor will perform the second stage. If the permissions at the second stage are more restrictive than the first then this creates a mismatch. To correct this mismatch detecting circuitry 30 will check intermediate physical addresses to see if the permissions at the second stage are more restrictive than at the first. If they are it will store a speculative mismatch in a cache 32, so that if the MMU initiates an intermediate address lookup instruction it can find out where the mismatch occurred and correct it more quickly. The mismatch detecting circuitry and the cache serve as speculative mismatch response provision circuitry and trigger a speculative translation provision operation in the event of a mismatch.

公开(公告)号：GB2539429B

公开(公告)日：2017-09-06

申请号：GB201510527

申请日：2015-06-16

Applicant: ADVANCED RISC MACH LTD

Inventor： JASON PARKER ,  RICHARD ROY GRISENTHWAITE ,  ANDREW CHRISTOPHER ROSE

IPC: G06F12/14 ,  G06F12/1036 ,  G06F21/74

Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).

公开(公告)号：FR3006786A1

公开(公告)日：2014-12-12

申请号：FR1355181

申请日：2013-06-05

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CARBON ALEXANDRE ,  LHUILLIER YVES ,  CHARLES HENRI PIERRE

IPC: G06F17/30 ,  G06F9/00 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/1036

Abstract: Accélérateur matériel pour la manipulation d'arbres rouges et noirs, chaque nœud d'un dit arbre comprenant un indicateur binaire de couleur, une clé et les adresses d'un nœud parent et de deux nœuds fils, ledit accélérateur comprenant - au moins deux registres dits registres de nœud (RN1, RN2), pouvant stocker l'ensemble des champs de données de deux nœuds d'un dit arbre ; et - des unités logiques (UC, UT) configurées pour recevoir d'un processeur (PROC) au moins une donnée d'entrée choisie parmi une adresse d'un nœud d'un dit arbre et une clé dite de référence, ainsi qu'au moins une instruction à exécuter ; pour exécuter ladite instruction en combinant des instructions élémentaires sur les données stockées dans lesdits registres de nœuds et pour fournir audit processeur au moins une donnée de sortie comprenant une adresse d'un dit nœud. Processeur et système informatique comprenant un tel accélérateur matériel.

公开(公告)号：GB0722686D0

公开(公告)日：2007-12-27

申请号：GB0722686

申请日：2007-11-20

Applicant: TRANSITIVE LTD

IPC: G06F12/0815 ,  G06F12/1036 ,  G06F12/109

Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.