公开(公告)号：JP2003077290A

公开(公告)日：2003-03-14

申请号：JP2002225924

申请日：2002-08-02

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： MATARRESE STELLA ,  FASOLI LUCA GIOVANNI

IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/808 ,  G11C29/81

Abstract: PROBLEM TO BE SOLVED: To provide a technique for replacing defective memory cells of a nonvolatile memory device according to the types of defects. SOLUTION: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements are capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.

Abstract translation: 要解决的问题：提供根据缺陷类型替换非易失性存储器件的有缺陷的存储单元的技术。 解决方案：公开了一种用于替换闪存器件中闪存单元的有缺陷的列的方法和电路。 电路包括多组存储元件，每组存储元件能够识别待替换的存储器单元的单个寻址列或主列线和与其相关联的常规列的存储器单元被替换。 在主列线和关联的常规列被识别用于由一组存储元件替换的情况下，该集合另外指示常规列是单个存储器单元块还是多个块中的常规列。 冗余电路基于存储在存储元件组中的信息在存储器访问操作期间执行替换操作。

公开(公告)号：JP2003077289A

公开(公告)日：2003-03-14

申请号：JP2002225117

申请日：2002-08-01

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： MATARRESE STELLA ,  FASOLI LUCA GIOVANNI

IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/808 ,  G11C29/81

Abstract: PROBLEM TO BE SOLVED: To improve a redundancy technique of a non-volatile memory device. SOLUTION: The technique is disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements are capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identify the addressed column of memory cells as being defective.

Abstract translation: 要解决的问题：改进非易失性存储器件的冗余技术。 解决方案：该技术被公开用于替换闪存设备中闪存单元的有缺陷的列。 电路包括多组存储元件，每组存储元件能够将存储器单元的任何块中的至少一列存储器单元识别为有缺陷的。 电路还包括控制电路，用于在肯定地确定一组存储元件将所寻址的存储器单元的列识别为有缺陷的情况下，用冗余列的存储器单元替换存储器单元的列。

公开(公告)号：JP2003067004A

公开(公告)日：2003-03-07

申请号：JP2002161448

申请日：2002-06-03

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： HILL JOHN P

IPC: G11B21/08 ,  G05B11/36 ,  G06F1/26 ,  G11B5/55 ,  G11B5/596

CPC classification number: G11B5/59605 ,  G06F1/26 ,  G11B5/5526

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method which make it possible to correct a driver at a faster rate.
SOLUTION: A power driver for driving a signal on a load uses a voltage- mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A lead compensator determines a compensated command to compensate for an admittance function of the load. The compensated commands are coupled to the voltage-mode driver, so that the voltage-mode driver generates a voltage output based upon the compensated command.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种能够以更快的速度校正驾驶员的系统和方法。 解决方案：用于驱动负载信号的电源驱动器使用电压模式驱动器。 系统处理器产生指示从电压模式驱动器所需的编程驱动信号的命令。 引线补偿器确定补偿指令以补偿负载的导纳功能。 补偿的命令被耦合到电压模式驱动器，使得电压模式驱动器基于补偿的指令产生电压输出。

公开(公告)号：JP2003008584A

公开(公告)日：2003-01-10

申请号：JP2002065556

申请日：2002-03-11

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： KARIM FARAYDON ,  NGUYEN ANH ,  DEY SUJIT

IPC: G06F13/36 ,  H04L12/28 ,  H04L12/42 ,  H04L12/56 ,  H04L12/66

CPC classification number: H04L49/15 ,  H04L49/109 ,  H04L49/352 ,  H04L49/357

Abstract: PROBLEM TO BE SOLVED: To provide an enhanced interconnection network technology for routing data packets. SOLUTION: The octagonal interconnection network is provided for routing data packets. The interconnection network comprises (1) eight switching circuits for transferring data packets with each other (2) eight sequential data links bidirectionally coupling the eight switching circuits in sequence to thereby form an octagonal ring configuration and (3) four crossing data links, wherein a first crossing data link bidirectionally couples a first switching circuit to a fifth switching circuit, a second crossing data link bidirectionally couples a second switching circuit to a sixth switching circuit, a third crossing data link bidirectionally couples a third switching circuit to a seventh switching circuit, and a fourth crossing data link bidirectionally couples a fourth switching circuit to a eighth switching circuit.

Abstract translation: 要解决的问题：提供一种用于路由数据包的增强型互连网络技术。 解决方案：提供八角互连网络用于路由数据包。 互连网络包括（1）用于彼此传送数据分组的八个切换电路（2）八个顺序数据链路，以顺序耦合八个切换电路，从而形成八角环配置，以及（3）四个交叉数据链路，其中a 第一交叉数据链路将第一开关电路双向耦合到第五开关电路，第二交叉数据链路将第二开关电路双向耦合到第六开关电路，第三交叉数据链路将第三开关电路双向耦合到第七开关电路， 并且第四交叉数据链路将第四开关电路双向耦合到第八开关电路。

公开(公告)号：WO2014131002A1

公开(公告)日：2014-08-28

申请号：PCT/US2014/018258

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： BASKER, Veeraraghavan, S. ,  LIU, Qing ,  YAMASHITA, Tenko ,  YEH, Chun-Chen

IPC: H01L21/20 ,  H01L21/336 ,  C23C16/42

CPC classification number: H01L29/41791 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming contacts in a semiconductor device includes forming (208) a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed (210) transversely to a longitudinal axis of the fins. The fins are merged (212) by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed (226) to expose the fins in the trenches. An interface layer is formed (228) over portions of the fins exposed in the trenches. Contact lines are formed (234) in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins.

Abstract translation: 一种用于在半导体器件中形成触点的方法包括在具有横向于鳍的纵向轴线形成（210）的栅极结构的基底的介电层上形成（208）多个基本上平行的半导体鳍。 翅片通过在翅片之间外延生长结晶材料而合并（212）。 场致电介质层沉积在鳍片和结晶材料上。 形成横向于翅片的纵向轴线延伸的沟槽（226）以暴露沟槽中的翅片。 界面层在暴露在沟槽中的翅片的部分上形成（228）。 接触线在与鳍片上的界面层的顶表面和翅片上的界面层的至少一部分侧表面接触的沟槽中形成（234）。

公开(公告)号：WO2012174169A2

公开(公告)日：2012-12-20

申请号：PCT/US2012/042325

申请日：2012-06-13

Applicant: NEO, TeckKhim ,  MIKULAN, Paul, I. ,  ROBINSON, Murray J. ,  ROSS, Rube M. ,  STMicroelectronics Asia Pacific Pte. Ltd. (Singapore) ,  STMicroelectronics, Inc.

Inventor： NEO, TeckKhim ,  MIKULAN, Paul, I. ,  ROBINSON, Murray J. ,  ROSS, Rube M.

CPC classification number: G06F21/73 ,  G06F21/44 ,  H04L9/3278

Abstract: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.

Abstract translation: 在一个实施例中，为了阻止或延迟伪装/克隆主机设备的替换部件，替换部件被提供有代码值。 代码值是从替换组件的至少一个物理参数的值生成的，并存储在替换组件上。 如果存储的代码值与参考代码值匹配，则主机设备确定替换组件是否可信。

公开(公告)号：WO2012170027A1

公开(公告)日：2012-12-13

申请号：PCT/US2011/039774

申请日：2011-06-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics, Inc. ,  POSSEME, Nicolas ,  GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud

Inventor： POSSEME, Nicolas ,  GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772

Abstract: The substrate successively comprises a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract translation: 基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。 半导体材料层和栅极图案被覆盖层覆盖。 第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。 覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

公开(公告)号：WO2005015753A3

公开(公告)日：2005-02-17

申请号：PCT/US2004/025324

申请日：2004-08-04

Applicant: STMICROELECTRONICS, INC. ,  NORSWORTHY, Steven, R. ,  THAM, Andrew ,  REDGRAVE, Jason, Rupert ,  GREY, Aubrey, Arthur

Inventor： NORSWORTHY, Steven, R. ,  THAM, Andrew ,  REDGRAVE, Jason, Rupert ,  GREY, Aubrey, Arthur

IPC: H03M1/00

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

公开(公告)号：WO2005015752A2

公开(公告)日：2005-02-17

申请号：PCT/US2004/025323

申请日：2004-08-04

Applicant: STMICROELECTRONICS, INC.

Inventor： NORSWORTHY, Steven, R. ,  REDGRAVE, Jason, Rupert

IPC: H04B

CPC classification number: H03H17/0628 ,  G06F5/14 ,  G06F2205/061 ,  H03H17/0614

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified imterpolator and decimator.

Abstract translation: 改进的插入器和抽取器装置和方法，包括在信号路径中添加弹性存储元件。 在一个示例性实施例中，弹性元件包括有利地允许吸收采样时钟中的短期变化的FIFO，并且还提供用于控制基于德耳塔西格玛调制的基于模N计数器的采样时钟发生器的反馈机制。 与delta-sigma调制器和计数器相结合的弹性元件创建了一个噪声形状的频率锁定环，无需额外的元件，从而得到简化的插入器和抽取器。

公开(公告)号：WO2005015746A2

公开(公告)日：2005-02-17

申请号：PCT/US2004/025223

申请日：2004-08-04

Applicant: STMICROELECTRONICS, INC.

Inventor： NORSWORTHY, Steven, R. ,  REDGRAVE, Jason, Rupert

IPC: H03M

CPC classification number: H03M3/392 ,  H03M3/394 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/498

Abstract: A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus generally comprises a noise-shaping coder having programmable coefficients, programmable coder order, programmable oversampling frequency, and/or programmable dither. In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally comprises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

Abstract translation: 公开了具有可变或可重新配置特性的噪声整形编码器。 在一个示例性实施例中，公开了一种用于信号调制的改进装置。 该装置通常包括具有可编程系数，可编程编码器顺序，可编程过采样频率和/或可编程抖动的噪声整形编码器。 在第二示例性实施例中，公开了一种用于实现噪声整形编码的改进方法。 该装置通常包括用于从一个订单编码器切换到另一个订单编码器的装置，以及切换过采样频率。