公开(公告)号：US09287254B2

公开(公告)日：2016-03-15

申请号：US14599167

申请日：2015-01-16

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06 ,  H01L29/74 ,  H01L29/747

CPC classification number: H01L27/0248 ,  H01L27/0262 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/7436 ,  H01L29/747

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.

Abstract translation: 电子设备包括第一设备终端和第二设备终端。 第一和第二晶闸管反向连接在两个器件端子之间。 第一和第二MOS晶体管分别耦合在两个晶闸管的两个NPN晶体管的导通电极（发射极和集电极）之间。 第三MOS晶体管耦合在两个晶闸管的两个NPN双极晶体管的发射极之间，第四个MOS晶体管耦合在两个晶闸管的两个PNP双极晶体管的基极之间。 栅极区域对于所有MOS晶体管是公共的，并且半导体衬底区域包括所有MOS晶体管的衬底。

公开(公告)号：US09270300B2

公开(公告)日：2016-02-23

申请号：US14177358

申请日：2014-02-11

Applicant: STMICROELECTRONICS S.A. ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Didier Belot ,  Yann Deval ,  Francois Rivet

IPC: H04B1/02 ,  H04B1/00 ,  H04B1/403 ,  H04L27/26 ,  H04B1/04

CPC classification number: H04B1/0021 ,  H04B1/0014 ,  H04B1/406 ,  H04B2001/0491 ,  H04L27/2639 ,  H04L27/2642

Abstract: A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.

Abstract translation: 一种用于产生射频信号的方法，其中待传输的信号被分解成不同频率的周期性基本信号的加权和。

公开(公告)号：US09236478B2

公开(公告)日：2016-01-12

申请号：US14193833

申请日：2014-02-28

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Yves Morand ,  Romain Wacquez ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7856

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract translation: 一种从包括半导体载体的氧化硅层上的半导体层的SOI型结构制造鳍式MOS晶体管的方法，该方法包括以下步骤：a）从半导体层的表面形成至少一个 沟槽，限定半导体层中的至少一个翅片，并一直延伸到半导体支撑体的表面; b）蚀刻位于翅片下方的氧化硅层的一部分的侧面，以在翅片下方形成至少一个凹部; 以及c）用在氧化硅上可选择性地蚀刻的材料填充所述凹部。

公开(公告)号：US09147725B2

公开(公告)日：2015-09-29

申请号：US13935813

申请日：2013-07-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot

IPC: H01L49/02 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L28/92 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/91

Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.

Abstract translation: 半导体器件包括具有正面和背面的衬底晶片。 在前面形成有前孔，在前孔中形成有层叠电容器。 在基板晶片的背面形成有后孔，露出至少一部分多层电容器。 使用前表面上的前电连接和后孔中的背电连接来与层叠电容器的由电介质层隔开的第一和第二导电板电连接。 前孔可以具有圆柱形或环形。

公开(公告)号：US20150214214A1

公开(公告)日：2015-07-30

申请号：US14610173

申请日：2015-01-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract translation: 电子器件包括具有阳极，阴极，设置在阳极侧的第一双极晶体管的晶闸管。 第二双极晶体管设置在阴极侧。 这两个双极晶体管被嵌套并连接在阳极和阴极之间。 MOS晶体管耦合在第二双极晶体管的集电极区域和发射极区域之间。 晶体管具有通过并入第二双极晶体管的基极区的至少一部分的电阻半导体区连接到阴极的栅极区。

公开(公告)号：US09008603B2

公开(公告)日：2015-04-14

申请号：US13707736

申请日：2012-12-07

Applicant: STMicroelectronics S.A.

Inventor： Floria Blanchet ,  Christophe Arricastres ,  Denis Pache

IPC: H04B1/10 ,  H01F5/00 ,  H01F30/04 ,  H01L23/522 ,  H01L27/01 ,  H01L49/02 ,  H03H7/42 ,  H01P5/10 ,  H01L23/66 ,  H03H7/01

CPC classification number: H01F5/003 ,  H01F21/12 ,  H01F27/2804 ,  H01F30/04 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/01 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01P5/10 ,  H03H7/1775 ,  H03H7/42 ,  H01L2924/00

Abstract: An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

Abstract translation: 集成电路包括具有N个通道的平衡不平衡型的集成变压器，其中N大于2.集成变压器在衬底上包括相互感应耦合并且分别与N个通道相关联的N个感应电路 。

公开(公告)号：US09007848B2

公开(公告)日：2015-04-14

申请号：US13754427

申请日：2013-01-30

Applicant: STMicroelectronics S.A.

Inventor： Anis Feki

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

CPC classification number: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract translation: 易失性存储器包括执行数据写入和读取操作的易失性存储器单元。 存储单元以行和列排列并且分布在每列的第一分离的存储单元组中。 对于每列，存储器包括专用于写操作并连接到列的所有存储器单元的写位线，以及专用于读操作的读位线。 每个读位线连接到第一组存储器单元之一的所有存储单元。 列中的每个存储单元连接到单个读取位线。

公开(公告)号：US08994138B2

公开(公告)日：2015-03-31

申请号：US13710260

申请日：2012-12-10

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles2) SAS

Inventor： François Roy ,  Sebastien Place

IPC: H01L27/146 ,  H01L31/18 ,  H04N5/76

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/1463 ,  H01L31/18 ,  H04N5/76

Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.

Abstract translation: 一种图像传感器，包括像素阵列，每个像素包括在第一导电类型的掺杂半导体材料的衬底中，在衬底的表面处具有第二导电类型的第一掺杂区域; 围绕所述第一区域的绝缘沟槽; 第一导电类型的第二掺杂区域，在衬底的表面上比衬底更重掺杂并且围绕沟槽; 第二导电类型的第三掺杂区域，与衬底一起形成光电二极管结，在第一和第二区域下方深度延伸到衬底中，并连接到第一区域; 以及介于所述第二和第三区域之间并与所述第一区域和/或与所述第三区域接触的比所述第二和第三区域更轻掺杂的第四区域。

公开(公告)号：US08928051B2

公开(公告)日：2015-01-06

申请号：US14084803

申请日：2013-11-20

Applicant: International Business Machines Corporation ,  STMicroelectronics S.A.

Inventor： Erwan Dornel ,  Pascal R. Tannhof ,  Denis Rideau

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/401 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底的沟道部分上提供栅极结构，其中栅极结构包括在半导体衬底的沟道部分上的至少一个栅极电介质和至少一个栅极导体 栅电介质。 所述至少一个栅极电介质的边缘部分在所述栅极结构的每一侧被去除，其中去除所述栅极电介质的所述边缘部分提供所述至少一个栅极导体的暴露的基极边缘和所述至少一个栅极导体的暴露的沟道表面 栅极结构底层的半导体衬底。 栅极结构的侧壁被氧化，其还氧化至少一个栅极导体的暴露的基极边缘和位于栅极结构下方的半导体衬底的暴露的沟道表面中的至少一个。

公开(公告)号：US20140347907A1

公开(公告)日：2014-11-27

申请号：US14280955

申请日：2014-05-19

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  David Turgis ,  Lorenzo Ciampolini

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C15/04

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract translation: 电子部件，包括三元内容可寻址存储器部件，被配置为将输入数据项与一组预先记录的参考数据字进行比较; 存储器组件包含以行和列布置的基本单元矩阵; 每行包含单元，每个单元记录一个参考数据字的一位; 给定列的单元专门用于比较输入数据字的相同位; 每个单元包含：存储表示参考数据位的数据的两个存储点; 连接到存储点的比较电路，如果输入数据位和存储在存储点中的数据，电位代表比较的比较点，并且还结合有公共比较电路，连接到所有比较电路的所有比较电路 或给定色谱柱的一部分细胞; 比较电路结合了来自输入数据字及其补码的位的终端。