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公开(公告)号:JP2014106973A
公开(公告)日:2014-06-09
申请号:JP2013238617
申请日:2013-11-19
Applicant: Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd. , Seoul National Univ R&Db Foundation , ソウル ナショナル ユニバーシティ アールアンドディビー ファウンデーション
Inventor: LEE MIN-JU , BERNHARD EGGER , LEE JAE-JIN , KIN EIRAKU , KIM HONG-GYU , KIM HONG-JUNE
IPC: G06F11/34
CPC classification number: G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
Abstract: PROBLEM TO BE SOLVED: To provide a performance measurement unit.SOLUTION: A performance measurement unit includes: a first event counter for recording an event count value indicating the number of events which occur in a processor core; and a second event counter for copying the event count value recorded in the first event counter. When the processor core enters a predetermined operation mode, the second event counter copies the event count value recorded in the first event counter. The predetermined operation mode is an operating system kernel mode. The performance measurement unit further includes a counter setting logic for selectively permitting the second event counter to copy the event count value recorded in the event counter.
Abstract translation: 要解决的问题:提供性能测量单元。解决方案:性能测量单元包括:第一事件计数器,用于记录指示出现在处理器核心中的事件数量的事件计数值; 以及用于复制记录在第一事件计数器中的事件计数值的第二事件计数器。 当处理器核心进入预定操作模式时,第二事件计数器复制记录在第一事件计数器中的事件计数值。 预定的操作模式是操作系统内核模式。 性能测量单元还包括用于选择性地允许第二事件计数器复制记录在事件计数器中的事件计数值的计数器设置逻辑。
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212.
公开(公告)号:JP5356396B2
公开(公告)日:2013-12-04
申请号:JP2010531080
申请日:2008-03-05
Inventor: ハイフェン チェン、 , グオフェイ ジアーン、 , 健治 吉平 , フゥイ ジャーン、 , シヤオチヤオ メン、
IPC: G06N5/04
CPC classification number: G06F9/44505 , G06F11/3409 , G06F11/3447 , G06F11/3452 , G06F2201/885
Abstract: A system and method for optimizing system performance includes applying sampling based optimization to identify optimal configurations of a computing system by selecting a number of configuration samples and evaluating system performance based on the samples. Based on feedback of evaluated samples, a location of an optimal configuration is inferred. Additional samples are generated towards the location of the inferred optimal configuration to further optimize a system configuration.
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公开(公告)号:JP4837445B2
公开(公告)日:2011-12-14
申请号:JP2006156982
申请日:2006-06-06
Applicant: 株式会社日立製作所
CPC classification number: G06F11/3495 , G06F3/0613 , G06F3/0617 , G06F3/0635 , G06F3/067 , G06F11/1008 , G06F11/3409 , G06F11/3485 , G06F2201/885
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214.
公开(公告)号:JP2010218367A
公开(公告)日:2010-09-30
申请号:JP2009065959
申请日:2009-03-18
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor: YAMAZAKI IWAO , HARA MITSUHARU , YAMANAKA EIJI
CPC classification number: G05B19/042 , G06F11/3466 , G06F11/3476 , G06F2201/88 , G06F2201/885
Abstract: PROBLEM TO BE SOLVED: To provide a technique for examining an operation state inside a processing apparatus when a user program is executed. SOLUTION: A processing apparatus includes a processor that executes an execution object program including a series of instructions. The processing apparatus is provided with: a log recording unit configured to record an operation log of the processing apparatus; a managing unit configured to control a recording operation performed by the log recording unit and to read the operation log recorded in the log recording unit; an input unit configured to detect, from among the series of instructions of the execution object program, a start instruction that starts a process for delivering a control instruction destined for the managing unit to the managing unit, and to deliver the control instruction to the managing unit in response to the start instruction; and an output unit configured to receive the operation log read by the managing unit from the managing unit. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题:提供一种用于在执行用户程序时检查处理装置内的操作状态的技术。 解决方案:处理装置包括执行包括一系列指令的执行对象程序的处理器。 该处理装置设置有:记录处理装置的操作日志的日志记录单元; 管理单元,被配置为控制由所述日志记录单元执行的记录操作并且读取记录在所述日志记录单元中的操作日志; 输入单元,被配置为从所述执行对象程序的一系列指令中检测开始指令,所述开始指令开始用于将用于所述管理单元的控制指令发送到所述管理单元的处理,并且将所述控制指令传递到所述管理 响应于开始指令的单位; 以及输出单元,被配置为从管理单元接收由管理单元读取的操作日志。 版权所有(C)2010,JPO&INPIT
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公开(公告)号:JP4554241B2
公开(公告)日:2010-09-29
申请号:JP2004074916
申请日:2004-03-16
Applicant: 富士通セミコンダクター株式会社
Inventor: 茂 木村
CPC classification number: G06F11/3466 , G06F8/4442 , G06F11/3612 , G06F12/0864 , G06F12/0875 , G06F2201/885
Abstract: A method of performing cache coloring includes the steps of generating function strength information in response to a dynamic function flow representing a sequence in which a plurality of functions are called at a time of executing a program comprised of the plurality of functions, the function strength information including information about runtime relationships between any given one of a plurality of functions and all the other ones of the plurality of functions in terms of a way the plurality of functions are called, and allocating the plurality of functions to memory space in response to the function strength information such as to reduce instruction cache conflict.
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公开(公告)号:JP4536717B2
公开(公告)日:2010-09-01
申请号:JP2006506116
申请日:2004-04-14
Inventor: アームストロング、ウィリアム、ジョセフ , カラ、ロナルド、ニック , シンハロイ、バララム , フロイド、マイケル、スティーヴン , ライトナー、ラリー、スコット
CPC classification number: G06F9/3851 , G06F9/50 , G06F11/3419 , G06F11/348 , G06F2201/88 , G06F2201/885
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公开(公告)号:JP4528307B2
公开(公告)日:2010-08-18
申请号:JP2006542904
申请日:2004-12-24
Applicant: インテル・コーポレーション
Inventor: アドル−タバタバイ、アリ−レーザ , スブラマネー、スレーヴィナス , セラーノ、モーリシオ , ハドソン、リチャード
CPC classification number: G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
Abstract: Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
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公开(公告)号:JP4421230B2
公开(公告)日:2010-02-24
申请号:JP2003207250
申请日:2003-08-12
Applicant: 株式会社日立製作所
CPC classification number: G06F11/3495 , G06F3/0605 , G06F3/061 , G06F3/0653 , G06F3/067 , G06F11/324 , G06F11/328 , G06F11/3409 , G06F11/3476 , G06F11/3485 , G06F2201/80 , G06F2201/815 , G06F2201/87 , G06F2201/885
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公开(公告)号:JP4371452B2
公开(公告)日:2009-11-25
申请号:JP37536198
申请日:1998-11-26
Applicant: ヒューレット・パッカード・カンパニーHewlett−Packard Company
Inventor: イー ウィール ウィリアム , エイ ウォールドスパージャー カール , イー ヒックス ジェームズ , エイ ディーン ジェフリー
CPC classification number: G06F11/3466 , G06F11/348 , G06F2201/81 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885
Abstract: An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.
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公开(公告)号:JP2009163773A
公开(公告)日:2009-07-23
申请号:JP2009104812
申请日:2009-04-23
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation IPC: G06F3/06 , G06F12/08 , G06F11/20 , G06F11/34 , G06F12/00 , G06F12/16 , G06F13/10 , G06F13/14 , G11B20/18 , H02H3/05
CPC classification number: G06F11/3485 , G06F3/0611 , G06F3/0632 , G06F3/0689 , G06F11/3419 , G06F2201/815 , G06F2201/885
Abstract: PROBLEM TO BE SOLVED: To solve the problem that a cache memory cannot be automatically configured with appropriate stripe size and alignment characteristics if the cache memory is separated from a virtualized RAID controller. SOLUTION: An apparatus has a memory operable with a virtualized RAID controller to determine an optimum I/O configuration by testing performance characteristics of a plurality of I/O operations, wherein the I/O operations include respectively writing a data block in the RAID controller, and the I/O configuration includes data length and data adjustment. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题:为了解决高速缓冲存储器与虚拟化RAID控制器分离的问题,高速缓冲存储器不能自动配置适当的条带大小和对齐特性。 解决方案:一种装置具有可利用虚拟化RAID控制器操作的存储器,以通过测试多个I / O操作的性能特征来确定最佳I / O配置,其中所述I / O操作包括分别将数据块写入 RAID控制器和I / O配置包括数据长度和数据调整。 版权所有(C)2009,JPO&INPIT
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