公开(公告)号：WO2007012053A1

公开(公告)日：2007-01-25

申请号：PCT/US2006/028256

申请日：2006-07-20

Applicant: STMICROELECTRONICS, S.R.L. ,  THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  SITI, Massimiliano ,  FITZ, Michael, P.

Inventor： SITI, Massimiliano ,  FITZ, Michael, P.

IPC: H04L1/06 ,  H04L25/03 ,  H04L1/00

CPC classification number: H04L25/06 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/06 ,  H04L25/03292 ,  H04L25/03331 ,  H04L2025/03414

Abstract: A method (200a-200b), apparatus (104), and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources (102, 102a-102t) are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources (102, 102a-102t) is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix.

Abstract translation: 提供了一种用于检测由多个源（102,102-102t）发送的数字调制码元的序列的方法（200a-200b），装置（104）和计算机程序。 确定单独处理接收矢量的同相和正交分量，信道增益和由多个源（102,102-102t）发送的发射矢量的实域表示。 处理真实域表示以获得三角矩阵。 另外，执行以下中的至少一个：（i）基于多个发送序列的降低的复杂度搜索，发送序列的硬判决检测和相应比特的解映射，以及（ii）产生位软输出 基于传输序列数量的复杂度降低的搜索值。 降低的复杂度搜索基于三角矩阵。

公开(公告)号：WO2007010570A1

公开(公告)日：2007-01-25

申请号：PCT/IT2005/000431

申请日：2005-07-22

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo ,  MASTROMATTEO, Ubaldo

Inventor： RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo ,  MASTROMATTEO, Ubaldo

IPC: G01L9/06 ,  G01L19/06

CPC classification number: G01L9/0054 ,  G01L9/0045 ,  G01L15/00

Abstract: In a pressure sensor (15) with double measuring scale: a monolithic body (16) of semiconductor material has a first main surface (16a), a bulk region (17) and a sensitive portion (33) upon which pressure (P) acts; a cavity (18) is formed in the monolithic body (16) and is separated from the first main surface (16a) by a membrane (19), which is flexible and deformable as a function of the pressure (P), and is arranged inside the sensitive portion (33) and is surrounded by the bulk region (17); a low-pressure detecting element (28) of the piezoresistive type, sensitive to first values of pressure (P), is integrated in the membrane (19) and has a variable resistance as a function of the deformation of the membrane (19); in addition, a high-pressure detecting element (29), also of a piezoresistive type, is formed in the bulk region (17) inside the sensitive portion (33) and has a variable resistance as a function of the pressure (P). The high­pressure detecting element (29) is sensitive to second values of pressure (P).

Abstract translation: 在具有双重测量标尺的压力传感器（15）中：半导体材料的整体（16）具有第一主表面（16a），主体区域（17）和压力（P）作用于其上的敏感部分 ; 在整体式主体（16）中形成空腔（18），并且通过膜（19）与第一主表面（16a）分离，该膜（19）作为压力（P）的函数是柔性和可变形的，并且布置 在所述敏感部分（33）的内部并且被所述主体区域（17）包围; 对第一压力值（P）敏感的压阻型低压检测元件（28）集成在膜（19）中，并具有作为膜（19）的变形的函数的可变电阻; 此外，在敏感部分（33）内的主体区域（17）中形成压阻型高压检测元件（29），并具有作为压力（P）的函数的可变电阻。 高压检测元件（29）对第二压力值（P）敏感。

公开(公告)号：WO2007006764A2

公开(公告)日：2007-01-18

申请号：PCT/EP2006/064035

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.r.l. ,  ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

Inventor： ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

公开(公告)号：WO2006128896A1

公开(公告)日：2006-12-07

申请号：PCT/EP2006/062812

申请日：2006-06-01

Applicant: STMICROELECTRONICS S.R.L. ,  PELLIZZER, Fabio ,  PIROVANO, Agostino

Inventor： PELLIZZER, Fabio ,  PIROVANO, Agostino

IPC: G11C11/56

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

Abstract: A method and apparatus for programming a phase change memory cell (2) is disclosed. A phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which the phase change material is crystalline and has a minimum resistance level, a second state ("00") in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell (2) in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter (D) through amorphous phase change material and a second programming pulse modifies the diameter (D) of the crystalline percolation path to program the phase change memory cell to the proper current level.

Abstract translation: 公开了一种用于编程相变存储单元（2）的方法和装置。 相变存储单元（2）包括具有第一状态（“11”）的相变材料的存储元件（10），其中所述相变材料是晶体并且具有最小电阻水平，第二状态（“ 00“），其中相变材料是非晶体并且具有最大电阻水平，以及在其间具有电阻水平的多个中间状态。 该方法包括使用编程脉冲来将相变存储器单元（2）编程在设置，复位或中间状态之一中。 为了在中间状态下进行编程，编程脉冲通过非晶相变材料产生具有平均直径（D）的结晶渗透路径，第二编程脉冲改变晶体渗滤路径的直径（D）以编程相变存储器单元 达到适当的当前水平。

公开(公告)号：WO2006122957A2

公开(公告)日：2006-11-23

申请号：PCT/EP2006/062394

申请日：2006-05-17

Applicant: STMicroelectronics S.r.l. ,  CURRO', Giuseppe

Inventor： CURRO', Giuseppe

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/336 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727

Abstract: MOSFET device formed in a semiconductor layer (12) overlaid by an insulated-gate structure (13, 14, 21) having at least two gate electrodes (14), of semiconductor material, which extend at a distance from one another and delimit between them a strip-shaped opening (15). The semiconductor layer accommodates a strip-shaped body region (19), which in turn accommodates a source region (20). A source-contact metal region (29) extends at least partially in the opening (15) and is in electrical contact with the body region (19) and the source structure (20, 25). The opening (15) is formed by elongated windows (15a) and contact cells (18) extending between pairs of consecutive elongated windows. The elongated windows (15) are filled with dielectric spacer material (26), and the metal contact structure (29) has first portions extending above the opening (15) at the elongated windows (15a) and second portions extending within the opening at the contact cells (18) and in direct electrical contact with the source structure (20, 25).

Abstract translation: MOSFET器件形成在由绝缘栅结构（13,14,21）重叠的半导体层（12）中，所述绝缘栅极结构（13,14,21）具有半导体材料的至少两个栅电极（14），它们彼此间隔开并在它们之间限定 带状开口（15）。 半导体层容纳条形体区域（19），其又容纳源区域（20）。 源极接触金属区域（29）至少部分地延伸在开口（15）中并且与体区域（19）和源结构（20,25）电接触。 开口（15）由细长的窗口（15a）和在成对的连续细长窗口之间延伸的接触单元（18）形成。 细长的窗口（15）填充有介电隔离材料（26），并且金属接触结构（29）具有在细长窗口（15a）处在开口（15）上方延伸的第一部分，并且在开口 接触电池（18）并与源结构（20,25）直接电接触。

公开(公告)号：WO2006117196A3

公开(公告)日：2006-11-09

申请号：PCT/EP2006/004109

申请日：2006-05-03

Applicant: STMICROELECTRONICS S.R.L. ,  VINCIGUERRA, Vincenzo ,  BEVILACQUA, Maria Fortuna ,  BUONOCORE, Francesco ,  COFFA, Salvatore

Inventor： VINCIGUERRA, Vincenzo ,  BEVILACQUA, Maria Fortuna ,  BUONOCORE, Francesco ,  COFFA, Salvatore

IPC: C01B31/02 ,  H01L21/768

Abstract: Method for growing carbon nanotubes having a determined chirality, comprising the steps of fragmentation of at least one initial carbon nanotube (30) having a determined chirality with obtainment of at least two portions, or seeds, of carbon nanotube, each one having one free growth end (32); supply of atoms of carbon (33) with autocatalyst addition of the atoms of carbon (33) at the free end (32) of each portion of nanotube (30) to determine an elongation, or growth, of the nanotube (30).

公开(公告)号：WO2006103246A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/061116

申请日：2006-03-28

Applicant: STMICROELECTRONICS S.R.L. ,  TRONCONI, Michele ,  CHIESA, Enrico ,  PASOLINI, Fabio

Inventor： TRONCONI, Michele ,  CHIESA, Enrico ,  PASOLINI, Fabio

IPC: H03H17/04

CPC classification number: H03H17/04 ,  G01P15/0891 ,  G01P15/18

Abstract: A digital high-pass filter (12) has an input (IN), an output (OUT), and a subtractor stage (20), having a first input terminal, a second input terminal and an output terminal. The first input terminal of the subtractor stage (20) is connected to the input (IN) of the digital high-pass filter (12) and the output terminal is connected to the output (OUT) of the digital high-pass filter (12). A recursive circuit branch (21) is connected between the output (OUT) of the digital high-pass filter (12) and the second input terminal of the subtractor stage (20). Within the recursive circuit branch (21) are cascaded an accumulation stage (23), constituted by an integrator circuit, and a divider stage (24). The cutoff frequency (f t ) of the digital high-pass filter (12) is variable according to a dividing factor (den) of the divider stage (24).

Abstract translation: 数字高通滤波器（12）具有输入（IN），输出（OUT）和减法器级（20），具有第一输入端，第二输入端和输出端。 减法器级（20）的第一输入端连接到数字高通滤波器（12）的输入（IN），输出端连接到数字高通滤波器（12）的输出端 ）。 递归电路分支（21）连接在数字高通滤波器（12）的输出（OUT）和减法器级（20）的第二输入端之间。 在递归电路分支（21）内，级联由积分器电路和分频器级（24）构成的累加级（23）。 数字高通滤波器（12）的截止频率（f ）根据分频器级（24）的分频因子（den）而变化。

公开(公告)号：WO2006089725A3

公开(公告)日：2006-08-31

申请号：PCT/EP2006/001591

申请日：2006-02-22

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/78

Abstract: Power semiconductor device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), and a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlying each other, the resistivity of each layer being different from that of the other layers, and wherein said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24).

公开(公告)号：WO2006069933A1

公开(公告)日：2006-07-06

申请号：PCT/EP2005/056921

申请日：2005-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  KARPOV, Ilya, V. ,  KUO, Charles C. ,  KIM, Yudong ,  ATWOOD, Greg

Inventor： KARPOV, Ilya, V. ,  KUO, Charles C. ,  KIM, Yudong ,  ATWOOD, Greg

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1683

Abstract: Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30) is formed within the same via (31) with the memory element (40, 130). In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer (28); in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide (40) used to form a memory element (130) and the lance material (30) is achieved by providing a pin hole opening in a dielectric (34), which separates the chalcogenide and the lance material.

Abstract translation: 在电介质（18,22）内的通孔内形成硫族化物选择装置（24,120）和硫族化物存储元件（40,130）。 结果，硫属化物被有效地捕获在通孔内，并且不需要胶或粘合层。 此外，避免了分层问题。 在与存储元件（40,130）相同的通孔（31）内形成喷枪材料（30）。 在一个实施例中，由于存在侧壁间隔件（28），喷枪材料制成更薄。 在另一个实施例中，没有使用侧壁间隔物。 用于形成存储元件（130）的硫族化物（40）与喷枪材料（30）之间的相对小的接触面积是通过在电介质（34）中设置一个销孔开口来实现的，所述电极隔开硫族化物和喷枪 材料。

公开(公告)号：WO2006067563A1

公开(公告)日：2006-06-29

申请号：PCT/IB2005/003606

申请日：2005-11-28

Applicant: STMICROELECTRONICS S.r.l. ,  POLONI, Angelo ,  SILVA, Filippo ,  VALLE, Stefano

Inventor： POLONI, Angelo ,  SILVA, Filippo ,  VALLE, Stefano

IPC: H04L25/02

CPC classification number: H04L25/0216 ,  H04L25/0212 ,  H04L27/2601

Abstract: In order to execute, as a function of a received signal (r), a procedure of channel estimation in a transmission channel with memory in a telecommunications system, there is envisaged an operation of estimation of a delay spread associated to said channel, said operation of estimation comprising calculation of a root mean square value ( τ rms ) of delay spread by means of a step of evaluation of crossings with a threshold level of a quantity associated to a transfer function of said channel. Said step of evaluation of crossings comprises evaluating a mean number of crossings ( λ 0 ) of the real and imaginary parts of said channel transfer function with a threshold level corresponding to the zero level. Preferential application is to OFDM telecommunications systems and in particular wireless. systems according to the IEEE 802.11a WLAN standard or the Hyperlanil WLAN standard.

Abstract translation: 为了根据接收信号（r）执行在电信系统中具有存储器的传输信道中的信道估计的过程，设想了与所述信道相关联的延迟扩展的估计的操作，所述操作 的估计包括计算均方根值（t