公开(公告)号：EP0632379A2

公开(公告)日：1995-01-04

申请号：EP94108649.8

申请日：1994-06-06

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Sicola, Stephen J. ,  Jackson, James P. ,  Oakey, Roger L. ,  Brame, Richard G. ,  Mclean, Ronald H. ,  Walker, Michael D. ,  Fava, Thomas F. ,  Adams, Thomas Gene

IPC: G06F11/16

CPC classification number: G06F11/2089 ,  G06F11/1008 ,  G06F11/1662 ,  G06F11/201 ,  G06F11/2097

Abstract: A fault tolerant storage controller utilizing tightly coupled dual controller modules. The controller modules each check to see if another controller module or cache module is present and, if so, then all configuration information with respect to the controller modules and attached devices are shared between them. Configuration information may be entered into either or both of the controller modules and the information is shared dynamically. Each cache module may be "locked" by an individual controller module to prevent the other controller module from inadvertently disturbing the contents of the other controller module's cache. During initialization, each controller module checks for the existence of an associated cache module and, if present, it is immediately "locked" by the controller module. Should a controller module fail or give an indication of a malfunction, the other controller module will disable or "kill" the malfunctioning controller module thereby resetting it and releasing any lock it may have had on its cache module. In those instances where the cache module is a write cache, the surviving controller module can resume operations where the malfunctioning controller module left off and complete any remaining writes to the disabled controller module's storage devices preventing the loss of any host computer data. The controller modules are tolerant of the other controller module failing and then rebooting and the sequence of events is detected and recognized by the surviving controller module such that it does not disable the one that failed. The dual controller modules communicate asynchronously to verify that they are each operational and to exchange and verify configuration information and to provide operational status dynamically.

Abstract translation: 采用紧耦合双控制器模块的容错存储控制器。 控制器模块检查是否存在另一个控制器模块或高速缓存模块，如果是，那么相关控制器模块和连接的设备的所有配置信息在它们之间共享。 可以将配置信息输入到任一个或两个控制器模块中，并且该信息被动态共享。 每个缓存模块可以由单独的控制器模块“锁定”，以防止其他控制器模块意外地干扰另一个控制器模块的高速缓存的内容。 在初始化期间，每个控制器模块检查是否存在关联的高速缓存模块，如果存在，控制器模块立即被“锁定”。 如果控制器模块出现故障或发出故障指示，则其他控制器模块将禁用或“中止”故障控制器模块，从而将其重置并释放其缓存模块上可能存在的任何锁定。 在缓存模块是写缓存的情况下，幸存的控制器模块可以恢复故障控制器模块停止的操作，并且完成对禁用的控制器模块的存储设备的任何剩余写入，从而防止任何主机计算机数据的丢失。 控制器模块容许其他控制器模块发生故障，然后重新启动，并且由幸存控制器模块检测和识别事件序列，使其不会禁用失败的控制器模块。 双控制器模块异步通信以验证它们是否可操作，并交换和验证配置信息并动态提供操作状态。

公开(公告)号：EP0305068B1

公开(公告)日：1994-10-26

申请号：EP88307203.5

申请日：1988-08-04

Applicant: International Business Machines Corporation

Inventor： Crockett, Robert Nelson ,  Kern, Robert Frederick ,  Miller, Arnold Grant ,  Norris, Richard Ernest ,  Pousson, Michael William, Jr. ,  Wagner, Robert E.

IPC: G06F13/12 ,  G06F15/16

CPC classification number: G06F11/201 ,  G06F13/126

公开(公告)号：EP0550853A3

公开(公告)日：1993-10-06

申请号：EP92121378.1

申请日：1992-12-16

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Baba, Hiroshi, c/o Mitsubishi Denki K.K.

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/201 ,  G11C29/88

Abstract: An array of disk drives stores information which is accessed through multiple channels by a host computer. Different channels are coupled to different sequences of disk drives. Different disk drives can be accessed simultaneously through different channels, enabling high data transfer rates. The same disk drive can be accessed through two different channels, enabling access even if one of the channels is busy or malfunctioning. According to one aspect of the invention the channels are divided into at least two mutually exclusive sets of channels, each set providing access to all the disk drives.

公开(公告)号：EP0532514A4

公开(公告)日：1993-10-06

申请号：EP91908123

申请日：1991-04-03

Applicant: MICRO TECHNOLOGY, INC.

Inventor： HENSON, LARRY, P. ,  GAJJAR, KUMAR ,  POWERS, DAVID, T. ,  IDLEMAN, THOMAS, E.

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11B20/18 ,  H04J15/00

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G06F2211/1057 ,  G11B20/1833

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

公开(公告)号：EP0550853A2

公开(公告)日：1993-07-14

申请号：EP92121378.1

申请日：1992-12-16

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Baba, Hiroshi, c/o Mitsubishi Denki K.K.

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/201 ,  G11C29/88

Abstract: An array of disk drives stores information which is accessed through multiple channels by a host computer. Different channels are coupled to different sequences of disk drives. Different disk drives can be accessed simultaneously through different channels, enabling high data transfer rates. The same disk drive can be accessed through two different channels, enabling access even if one of the channels is busy or malfunctioning. According to one aspect of the invention the channels are divided into at least two mutually exclusive sets of channels, each set providing access to all the disk drives.

Abstract translation: 一组磁盘驱动器存储由主机通过多个通道访问的信息。 不同的通道耦合到不同的磁盘驱动器序列。 可以通过不同的通道同时访问不同的磁盘驱动器，实现高数据传输速率。 可以通过两个不同的通道访问同一个磁盘驱动器，即使其中一个通道正忙或故障，也可以进行访问。 根据本发明的一个方面，信道被分成至少两个互斥的信道集合，每个信道集合提供对所有磁盘驱动器的访问。

公开(公告)号：EP0414729A4

公开(公告)日：1993-01-13

申请号：EP89904939

申请日：1989-04-19

Applicant: AMDAHL CORPORATION

Inventor： KRAKAUER, ARNO, STARR ,  GAWLICK, DIETER ,  COLGROVE, JOHN ALAN ,  WILMOT, RICHARD, BYRON, II

IPC: G06F3/06 ,  G06F9/50 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/00 ,  G06F12/08 ,  G06F15/16 ,  G06F17/30 ,  G06F13/00 ,  G06F11/08

CPC classification number: G06F11/2089 ,  G06F9/50 ,  G06F11/1008 ,  G06F11/201 ,  G06F11/2056 ,  G06F11/2094 ,  G06F12/08 ,  G06F15/161 ,  G06F17/30067 ,  Y10S707/99953

Abstract: A file system for managing data files for access by a plurality of users of a data processing system that includes internal storage (41) for buffering, external storage (44), and a file user interface (I) by which the plurality of users request access to data files. A first level, coupled to the file user interface (41) for temporary storage of data to be accessed by the plurality of users, and generates requests for transactions with external storage (44) in support of such allocations. A second level is coupled to the first level and the external storage (44) and responds to the request for transactions with the external storage (44) for managing the transactions for storage of data to, and retrieval of data from, the external storage (44).

公开(公告)号：EP0434532A1

公开(公告)日：1991-06-26

申请号：EP90403616.7

申请日：1990-12-14

Applicant: BULL S.A.

Inventor： Carteau, Daniel ,  Schreck, Philippe

IPC: G06F11/20

CPC classification number: G06F11/201 ,  G06F11/2089

Abstract: 1. Procédé sécurisé d'écriture rapide d'informations pour au moins un dispositif de mémoire de masse (DMM₁) appartenant à un système informatique comportant au moins un hôte central (H₁, H₂), deux unités de contrôle (UC₁, UC₂) à alimentations électriques indépendantes (ALIM₁, ALIM₂, BAT₁, BAT₂) connectées à deux bus de type parallèle (B₁, B₂).
Selon l'invention, le procédé est caractérisé en ce que l'hôte (H₁, H₂) étant relié à chacun des deux bus par au moins un premier adaptateur hôte (HA₁, HA₂) appartenant à la première unité de contrôle (UC₁, UC₂) comportant un premier tampon hôte (MTH₁, MTH₂), la mémoire de masse (D₁ à D₅) étant reliée à chacun des deux bus par un premier et un second adaptateur mémoire de masse (DA₁, DA₂) appartenant respectivement à la première et à la seconde unité de contrôle comportant respectivement un premier et un second tampon mémoire (MTD₁, MTD₂),

I - On mémorise le bloc de données à écrire dans les premier tampon hôte (MTH₁, MTH₂) et tampon mémoire (MTD₁, MTD₂),
II - Le premier adaptateur mémoire de masse (DA₁, DA₂) réserve la mémoire de masse (D₁ à D₅, D₆ à D₁₀),
III- L'adaptateur mémoire de masse (DA₁) en informe ensuite l'adaptateur hôte (HA₁) qui envoie alors un signal d'acquittement à l'hôte central (H₁),
IV - L'opération d'écriture du bloc dans son entier est effectuée dans la mémoire de masse, sous la conduite du premier adaptateur mémoire de masse (DA₁), ou du second si le premier est défectueux.

Applicable aux sous-systèmes de mémoire de masse.

Abstract translation: 1.一种用于至少一个大容量存储设备（DMM1），属于一个计算机系统，包括至少一个中心主机（H1，H2），两个控制单元（UC1，UC2）具有独立电气用品（Alim1，ALIM2，BAT1方法 ，BAT2）连接至两个平行的类型总线（B1，B2）。 ... 。根据本发明，该方法DASS主机（H1，H2）由至少一个第一主机适配器被连接到每两个总线的属于所述第一控制单元（HA 1，HA 2）（ UC1，UC2），包括第一主缓冲液（MTH1，mth2），大容量存储（D1至D5）由第一和第二质量的存储适配器（DA1，DA2）分别属于第一被连接到每两个总线的 和第二控制单元分别包括第一和第二存储缓冲器（MTD1，mtd2）...... I - 要被写入存储在第一主机缓冲器数据（MTH1，mth2）和存储缓冲区的块（MTD1， mtd2）... II - 第一个大容量存储适配器（DA1，DA2）保留在大容量存储（D1至D5，D6至D10）... III - 大容量存储适配器（DA1）下一个通知主机适配器（HA 1）其 其下一个发送到结清信号到中央主机（H1）... IV - 运算整个块的写入到大容量存储进行未 如果第一有缺陷的第一质量的存储适配器（DA1），或第二主持的。 ...... 应用到大容量存储子系统。 ... ...

公开(公告)号：EP0305068A3

公开(公告)日：1990-06-27

申请号：EP88307203.5

申请日：1988-08-04

Applicant: International Business Machines Corporation

Inventor： Crockett, Robert Nelson ,  Kern, Robert Frederick ,  Miller, Arnold Grant ,  Norris, Richard Ernest ,  Pousson, Michael William, Jr. ,  Wagner, Robert E.

IPC: G06F13/12 ,  G06F15/16

CPC classification number: G06F11/201 ,  G06F13/126

Abstract: A plurality of host processors share access to a peripheral data storage sub-system and each have program means for controlling asynchronous operations of the sub-system. Control blocks in each of the host processors are addressably linked together for enabling inferred access to a unit control block (UCB) for any of a plurality of peripheral devices in the sub-system. The sub-system selectively groups some of the devices such that only devices designated as primary devices are addressably accessible by host processor application programs. Other devices in the respective groups are secondary devices and are accessed by the sub-system whenever the primary device in the same group cannot perform a host processor commanded operation. Means are provided for identifying the secondary devices to all of the host processors.

公开(公告)号：EP0059838B1

公开(公告)日：1988-06-01

申请号：EP82100723.4

申请日：1982-02-02

Applicant: International Business Machines Corporation

Inventor： Videki II, Edwin Raymond

IPC: G06F13/00

CPC classification number: G06F11/201 ,  G06F13/122 ,  G06F13/4022

公开(公告)号：EP1662369B1

公开(公告)日：2017-12-06

申请号：EP05253250.4

申请日：2005-05-26

Applicant: FUJITSU LIMITED

Inventor： Ohara, Shigeyoshi c/o Fujitsu Limited ,  Masuyama, Kazunori c/o Pfu Limited

IPC: G06F3/06 ,  G06F12/0866 ,  G06F11/20

CPC classification number: G06F3/0689 ,  G06F3/0605 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0665 ,  G06F3/0683 ,  G06F11/201 ,  G06F11/2089 ,  G06F12/0866

Abstract: A storage system has a plurality of control modules (4-0, 4-1, ..., 4-7) for controlling a plurality of storage devices (2-0, 2-1, ... , 2-25), which make mounting easier whilst maintaining a low latency response even if the number of control modules increases. A plurality of storage devices are connected to each control module using back end routers (5-0, 5-1, ..., 5-7), so that redundancy for all the control modules to access all the storage devices is maintained. The control modules and the back end routers are connected by a serial bus, which has a small number of signal lines, the interface being constituted by a back panel (7). This configuration can easily be scaled without mounting problems.