受信装置およびハイブリッドARQ通信システム
    222.
    发明申请
    受信装置およびハイブリッドARQ通信システム 审中-公开
    接收和混合APQ通信系统

    公开(公告)号:WO2004107639A1

    公开(公告)日:2004-12-09

    申请号:PCT/JP2003/006604

    申请日:2003-05-27

    CPC classification number: H04L1/1812 H04L1/1819 H04L1/1845 H04L1/201

    Abstract:  受信機(2)は、送信機から送信されたデータを受信する。受信したデータは、H−ARQバッファ(36)に保存され、平均値演算部(32)によりデータの絶対値の平均値が求められる。H−ARQ合成判定処理部(34)は、H−ARQバッファ(36)に保存された既存のデータの平均値M0と、再送された再送データの平均値M1とを所定の条件で比較し、信頼度の高低を判定する。信頼度が所定の値よりも高いときには、既存のデータと再送データとを合成器(37)により合成処理した後、誤り訂正復号部(39)により誤り訂正し、復調ビットを出力させる。誤りが多いときにはデータを再送要求する。信頼度が所定の値よりも低いときには、既存のデータと再送データとを合成せず、直ちにデータを再送要求する。

    Abstract translation: 接收机(2)接收从发射机发送的数据。 所接收的数据被存储在H-ARQ缓冲器(36)中,使得数据的绝对值的平均值由平均值操作部分(32)确定。 H-ARQ组合判断部(34)将存储在H-ARQ缓冲器(36)中的现有数据的平均值(MO)与预定条件下的重发数据的平均值(M1)进行比较, 可靠性程度。 当可靠性超过预定值时,现有数据和重发数据由组合器(37)组合,然后由纠错解码部分(39)校正错误(如果有的话)以输出解码的比特。 当有很多错误时,请求重传数据。 当可靠性低于预定值时,请求将数据立即重传,而不必组合现有数据和重发数据。

    OUTER-LOOP POWER CONTROL FOR WIRELESS COMMUNICATION SYSTEMS
    223.
    发明申请
    OUTER-LOOP POWER CONTROL FOR WIRELESS COMMUNICATION SYSTEMS 审中-公开
    无线通信系统的外环功率控制

    公开(公告)号:WO2004075496A2

    公开(公告)日:2004-09-02

    申请号:PCT/US2004/004790

    申请日:2004-02-18

    CPC classification number: H04L1/0039 H04L1/201

    Abstract: Systems and methods for evaluating packets and frames in a wireless communication system having multiple reverse-link channels including a spontaneous, burst oriented transmission channel and its corresponding rate indicator channel. One embodiment comprises a base station monitoring the rate indicator channel(510), decoding the rate indicator channel using a maximum likelihood decoder and detecting the presence of a packet on the rate indicator channel by comparing a likelihood with a threshold(520), and analyzing the validity of a frame on the burst oriented channel based on the presence and content of packets received on the rate indicator channel (530).

    Abstract translation: 在具有多个反向链路信道的无线通信系统中评估分组和帧的系统和方法,包括自发的突发定向传输信道及其对应的速率指示信道。 一个实施例包括监视速率指示符信道(510)的基站,使用最大似然解码器解码速率指示符信道,并通过将似然率与阈值(520)进行比较来检测速率指示符信道上的分组的存在(520) 基于在速率指示信道(530)上接收到的分组的存在和内容,基于突发定向信道上的帧的有效性。

    SYSTEM AND METHOD FOR DTX FRAME DETECTION
    224.
    发明申请
    SYSTEM AND METHOD FOR DTX FRAME DETECTION 审中-公开
    用于DTX帧检测的系统和方法

    公开(公告)号:WO0203588A3

    公开(公告)日:2002-06-20

    申请号:PCT/US0120819

    申请日:2001-06-28

    Applicant: QUALCOMM INC

    CPC classification number: H04L1/20 H04J3/14 H04J3/17 H04L1/201

    Abstract: A system and method for dectecting discontinuous transmission (DTX) frames. The inventive method includes the steps of receiving data transmitted in a pluralitz of frames (62); classifzing each of the frames (63); analyzing the classification of a number of successive frames of the received data and providing a metric with respect thereto; and determining, in response to the metric, if a frame is a discontinuous frame (66). In the illustrative embodiment, the step of classifzing includes the step of error checking the frames using a cyclic redundancz check (CRC) error checking protocol. The received frames are classified as good frames (G), erasureframes (E), or discontinuous frames (D). A numerical value is assigned toe ach of the frames based on the classification thereof. Next, the frames are filtered tp provice an output Yn=Yn-1+Xn where 'n' is a frame number, Yn is the filter output for a given frame n, Yn-1 is the filter output for a previous frame, and Xn is a stream of input frames. A threshold is set for the output Yn to facilitate the detection of discontinuous frames. That is, a detection of a discontinuous transmisson frame is indicated when a frame is classified as an 'erasure' and the filter output exceeds the threshold. On the detection of a discontinuous frame, the classification of the frame is changed from 'erasure' to 'discontinuous'. By reclassifying improperly classified erasure frames, the mobile receiver is inhibited from requesting retransmission of the frames of a change in the transmit power level. Consequently, network throughput and capacity are optimized and system power is conserved.

    Abstract translation: 一种用于检测不连续传输(DTX)帧的系统和方法。 本发明的方法包括以下步骤:接收以多个帧(62)发送的数据; 分类每个帧(63); 分析接收到的数据的多个连续帧的分类并提供关于其的度量; 以及响应于该度量确定帧是否是不连续帧(66)。 在说明性实施例中,分类步骤包括使用循环冗余校验(CRC)错误校验协议来错误检查帧的步骤。 接收的帧被分类为好帧(G),擦除帧(E)或不连续帧(D)。 基于其分类将数值分配给多个帧。 接下来,对帧进行滤波,以提供输出Y n = Y n-1 + X n,其中'n'是帧号,Y n是给定帧n的滤波器输出,Y n-1是前一帧的滤波器输出, Xn是输入帧的流。 为输出Yn设置阈值以便于检测不连续的帧。 也就是说,当帧被分类为“擦除”并且滤波器输出超过阈值时,指示不连续传输帧的检测。 在检测到不连续的帧时,帧的分类从“擦除”变为“不连续”。 通过重新分类不正确分类的擦除帧,禁止移动接收机请求重发发射功率电平变化的帧。 因此,网络吞吐量和容量得到优化,系统功率得到节约。

    METHOD AND APPARATUS FOR IMPROVED DETECTION OF RATE ERRORS IN VARIABLE RATE RECEIVERS
    225.
    发明申请
    METHOD AND APPARATUS FOR IMPROVED DETECTION OF RATE ERRORS IN VARIABLE RATE RECEIVERS 审中-公开
    改进检测可变速率接收机中速率误差的方法和装置

    公开(公告)号:WO0247316A2

    公开(公告)日:2002-06-13

    申请号:PCT/US0144574

    申请日:2001-11-29

    Applicant: QUALCOMM INC

    CPC classification number: H04L1/08 H04L1/0046 H04L1/201

    Abstract: A system and method for detection of rate determination algorithm errors in variable rate communications system receivers. The disclosed embodiments prevent rate determination algorithm errors from causing audible artifacts such as screeches or beeps. The disclosed system and method detects frames with incorrectly determined data rates and performs frame erasure processing and/or memory state clean up to prevent propagation of distortion across multiple frames. Frames with incorrectly determined data rates are detected by checking illegal rate transitions, reserved bits, validating unused filter type bit combinations and analyzing relationships between fixed code-book gains and linear prediction coefficient gains.

    Abstract translation: 一种用于在可变速率通信系统接收机中检测速率确定算法错误的系统和方法。 所公开的实施例防止速率确定算法错误引起可听见的伪影,例如吱吱声或哔哔声。 所公开的系统和方法检测具有错误确定的数据速率的帧,并执行帧擦除处理和/或存储器状态清理,以防止跨多个帧的失真传播。 通过检查非法速率转换,保留位,验证未使用的滤波器类型位组合以及分析固定码本增益和线性预测系数增益之间的关系来检测具有不正确确定的数据速率的帧。

    VITERBI DECODER WITH REDUCED SIZE PATH METRIC MEMORY
    227.
    发明申请
    VITERBI DECODER WITH REDUCED SIZE PATH METRIC MEMORY 审中-公开
    具有减小尺寸路径公制存储器的VITERBI解码器

    公开(公告)号:WO00008768A1

    公开(公告)日:2000-02-17

    申请号:PCT/US1999/017658

    申请日:1999-08-04

    Abstract: A serial Viterbi decoder for use in a mobile telephone comprising a RAM for storing state metrics, which needs to store only 2 metrics, when k is the contraint length of the code, rather than 2 metrics as required with previous implementations in which new state metrics and old state metrics were stored in two different memories. The ACS includes a left rotator receiving a signal identifying the current encoder state of the ACS and a counter signal incremented each time the ACS has cycled through all permissible states. The left rotator calculates a read address for reading the correct state metric corresponding the current encoder state from the state RAM. The read address is routed through a set of delay registers each driven by a clock signal which pulses every other clock cycle. The read signal and the delayed read signal are both routed into a multiplexor, the output of which is applied as the read or write address-input of the state RAM. A write enable signal is applied to the state RAM using the inverted clock system. Hence, the state RAM reads and writes state metrics from the same memory address with the address determined by the left rotator and with the write operation delayed with respect to the read operation.

    Abstract translation: 一种在移动电话中使用的串行维特比解码器,其包括用于存储状态度量的RAM,其需要仅存储2个k-1度量,当k是代码的相对长度,而不是根据需要的2 k个度量 其中先前的实现将新的状态度量和旧状态度量存储在两个不同的存储器中。 ACS包括左旋转器,其接收识别ACS的当前编码器状态的信号,以及每当ACS循环通过所有允许状态时递增的计数器信号。 左旋转器计算从状态RAM读取对应于当前编码器状态的正确状态度量的读取地址。 读取地址通过一组延迟寄存器进行路由,每个延迟寄存器由每隔一个时钟周期脉冲的时钟信号驱动。 读信号和延迟读信号都被路由到多路复用器,其输出被应用为状态RAM的读或写地址输入。 使用反相时钟系统将写使能信号施加到状态RAM。 因此,状态RAM从具有由左旋转器确定的地址的相同存储器地址读取和写入状态度量,并且相对于读取操作延迟写入操作。

    A METHOD AND AN ARRANGEMENT FOR FRAME DETECTION QUALITY ESTIMATION IN THE RECEIVER OF A RADIO COMMUNICATION SYSTEM
    228.
    发明申请
    A METHOD AND AN ARRANGEMENT FOR FRAME DETECTION QUALITY ESTIMATION IN THE RECEIVER OF A RADIO COMMUNICATION SYSTEM 审中-公开
    无线电通信系统接收机框架检测质量估计的方法和装置

    公开(公告)号:WO1994000938A1

    公开(公告)日:1994-01-06

    申请号:PCT/SE1993000476

    申请日:1993-05-28

    CPC classification number: H04L1/201 H04B7/2643 H04L1/20 H04L2001/0098

    Abstract: A method and an arrangement for quality estimation when detecting an information frame, for instance a speech frame transmitted in a radio communication system in accordance with time division multiple access (TDMA), although the method can also be applied with frequency divided radio systems. There is used the soft information available in the radio receiver (RM, DM, DI, KD) which is intended to detect the speech frame and process this signal information in accordance with those principles applicable to known neural nets. Prior to use, the neural net (NT) is aligned to the radio communication system concerned. The invention enables better information relating to possible error in the speech frame to be delivered to error correcting units (TD) in the radio receiver.

    Abstract translation: 当检测到信息帧(例如,根据时分多址接入(TDMA)的无线电通信系统中发送的语音帧)时,虽然该方法也可以应用于分频无线电系统,但是用于质量估计的方法和装置。 使用无线电接收机(RM,DM,DI,KD)中可用的软信息,其旨在检测语音帧,并根据适用于已知神经网络的原则处理该信号信息。 在使用之前,神经网络(NT)与所涉及的无线电通信系统对准。 本发明能够使与语音帧中的可能的错误相关的更好的信息传送到无线电接收机中的纠错单元(TD)。

    CODED SIDELINK FEEDBACK FOR IMPROVED RELIABILITY

    公开(公告)号:US20240106570A1

    公开(公告)日:2024-03-28

    申请号:US17953180

    申请日:2022-09-26

    CPC classification number: H04L1/0073 H04L1/0013 H04L1/201 H04W76/14

    Abstract: Methods, systems, and devices for wireless communications are described herein. A user equipment (UE) may generate a set of feedback bits corresponding to sidelink messages received via one or more sidelink channels. The UE may transmit a first sidelink message via a first feedback resource of a physical sidelink feedback channel occasion. The first sidelink message may include a first subset of the feedback bits. The UE may transmit at least two additional sidelink feedback messages via respective feedback resources. The first additional sidelink feedback message may include the first subset of feedback bits and a second subset of feedback bits encoded using an erasure coding function.

    Rule compilation schemes for fast packet classification

    公开(公告)号:US11929837B2

    公开(公告)日:2024-03-12

    申请号:US17678074

    申请日:2022-02-23

    CPC classification number: H04L1/201 G06F16/2255 G06F16/285

    Abstract: A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

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