公开(公告)号：US20040230736A1

公开(公告)日：2004-11-18

申请号：US10760631

申请日：2004-01-20

Applicant: STMicroelectronics S.A.

Inventor： Bruno Leconte ,  Sebastien Zink ,  Paola Cavaleri

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract translation: 地址解码器有选择地应用于存储器阵列的字线，根据应用于解码器的字线地址而变化的可变极性，负或正的各个信号。 解码器包括传送用于选择可变极性字线组的信号的组解码器，传送用于选择可变极性字线子组的信号的至少一个子组解码器，以及字线驱动器，每个字线驱动器包括用于复用组和子组 选择信号，用于选择并选择性地将这些信号中的一个施加到字线。 优点：减少解码器的端接元件的尺寸与减少闪存中技术间距有关。

公开(公告)号：US20040221141A1

公开(公告)日：2004-11-04

申请号：US10779855

申请日：2004-02-17

Applicant: STMicroelectronics S.A.

Inventor： Gosagan Padmanabhan ,  Dragos Davidescu ,  Franck Roche

IPC: G06F009/30

CPC classification number: G06F9/30123 ,  G06F9/3004 ,  G06F9/4486 ,  G06F9/461

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract translation: 本发明涉及一种用于管理包括中央处理单元和存储器阵列的微处理器的堆叠的方法，所述中央处理单元包括包含上下文数据的寄存器和堆栈指针，所述堆栈是用于保存的存储器阵列的区域 从第一程序切换到第二程序时的上下文数据。 根据本发明，该方法包括保存包含在根据存储在要保存的寄存器中的至少一个标志的值而变化的可变数目的寄存器中的上下文数据。 优点：优化堆栈的填充以及可以交错的子程序数量。

公开(公告)号：US20040210730A1

公开(公告)日：2004-10-21

申请号：US10700361

申请日：2003-11-03

Applicant: STMicroelectronics S.A.

Inventor： Pierre Marty ,  Rey Gaelle ,  Pascal Chauvet

IPC: G06F012/00

CPC classification number: G11C7/22 ,  G06F13/1673

Abstract: A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.

Abstract translation: 一种用于控制存储器的电路，所述存储器包括不能同时访问的至少两个区域，所述电路包括用于为每个区域分别存储一系列读取和/或写入指令的第一电路，以及用于检测第一 用于第一区域的指令是第一区域不能接收其他指令的周期之后的预定指令，以及在该周期期间向另一个存储区域提供指令的第三电路。

公开(公告)号：US20040143805A1

公开(公告)日：2004-07-22

申请号：US10699613

申请日：2003-10-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Arnaud Deleule

IPC: G06F009/45 ,  H01L029/06

CPC classification number: G03F1/38 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for determining the version of metal mask utilized for producing a given metal layer (Metal3) in an integrated circuit including a plurality of metal layers (Meta0, . . . , Metal3), and any modification made to the given metal layer (Metal3) requiring generation of a new version of the corresponding metal mask. The device includes a cell (Cell) integrated into the metal layer (Metal3) including at least a first voltage source (Vdd) for supplying a first voltage level, at least a second voltage source (GND) for supplying a second voltage level, and an output bus composed of at least one conductor wire (S1, S2) connected selectively to one of the first and second voltage sources as a function of the version of metal mask used to produce the metal layer, so as to generate a binary output signal representative of the mask version utilized.

Abstract translation: 一种用于确定用于在包括多个金属层（Meta0，...，Metal3）的集成电路中制造给定金属层（Metal3）的金属掩膜版本的装置，以及对给定金属层（Metal3 ）需要产生相应金属掩模的新版本。 该装置包括集成到金属层（Metal3）中的单元（Cell），其包括用于提供第一电压电平的至少第一电压源（Vdd），用于提供第二电压电平的至少第二电压源（GND）;以及 一个输出总线，其由至少一个导体线（S1，S2）组成，该导体线选择性地连接到第一和第二电压源中的一个，作为用于产生金属层的金属掩模的形式的函数，以便产生二进制输出信号 代表使用的掩模版本。

公开(公告)号：US20040136238A1

公开(公告)日：2004-07-15

申请号：US10697957

申请日：2003-10-30

Applicant: STMicroelectronics S.A.

Inventor： Sylvie Wuidart ,  Luc Wuidart

IPC: G11C011/34

CPC classification number: G11C17/18 ,  G11C11/5692 ,  G11C17/14

Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.

Abstract translation: 具有至少两个可检测状态的存储单元是未编程状态，包括串行施加读取电压的两个端子之间的至少一个第一分支，包括：预读阶段，并联包括两个可切换电阻器 具有第一预定差值的不同值; 以及由多晶硅编程电阻器形成的编程阶段，编程电阻的端子可由能够导致其值不可逆地减小的编程电路访问。

公开(公告)号：US20040119452A1

公开(公告)日：2004-06-24

申请号：US10728582

申请日：2003-12-04

Applicant: STMicroelectronics S.A.

Inventor： Arnaud Florence ,  Jerome Heurtier ,  Franck Galtie

IPC: G05F001/40

CPC classification number: H03K7/08

Abstract: A generator of at least one pulse width modulated signal, including: a generator of a sawtooth signal a generator of high and low reference signals defining, based on a set-point signal, a linear range of each ramp of the sawtooth signal at least one element of comparison of the sawtooth signal with each of the reference signals and at least one element of logic combination of the comparison results, providing the pulse width modulated signal.

Abstract translation: 一种至少一个脉冲宽度调制信号的发生器，包括：锯齿波信号的发生器，高和低参考信号的发生器，其基于设定点信号定义锯齿波信号的每个斜坡的线性范围，至少一个 锯齿波信号与每个参考信号的比较元件以及比较结果的逻辑组合的至少一个元件，提供脉宽调制信号。

公开(公告)号：US20040108571A1

公开(公告)日：2004-06-10

申请号：US10716249

申请日：2003-11-18

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L029/00

CPC classification number: H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract translation: 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。

公开(公告)号：US20040068383A1

公开(公告)日：2004-04-08

申请号：US10610343

申请日：2003-06-30

Applicant: STMICROELECTRONICS S.A. ,  STMICROELECTRONICS LTD

Inventor： Hitesh Shah ,  Laurent Perier

IPC: G06F019/00

CPC classification number: H03L1/00

Abstract: A chip includes CPU (12), memories (13,14) for programs and data, peripheral units (18,19) for interacting with the outside world, and an internal RC oscillator (17) for providing clock signals. One of the peripheral units (18) includes a timer counter incremented at a frequency derived from the RC oscillator. The method does not try to change the frequency of the RC oscillator. Instead, an external calibration source (21) is connected to a capture input of the timer unit to provide a signal having a reference frequency, e.g. the mains frequency. The counter is sampled on active edges of that signal, and the sampled values are processed to derive a calibration ratio. After these calibration steps, a software correction is applied to parameters handled by programs stored in memory based on the calibration ratio to compensate for frequency variations of the RC oscillator.

Abstract translation: 芯片包括CPU（12），用于程序和数据的存储器（13,14），用于与外界相互作用的外围单元（18,19）和用于提供时钟信号的内部RC振荡器（17）。 外围单元（18）中的一个包括以从RC振荡器得到的频率递增的定时器计数器。 该方法不会改变RC振荡器的频率。 相反，外部校准源（21）连接到定时器单元的捕获输入，以提供具有参考频率的信号，例如， 电源频率。 在该信号的有效边沿对计数器进行采样，并处理采样值以导出校准比。 在这些校准步骤之后，基于校准比率对存储在存储器中的程序处理的参数应用软件校正以补偿RC振荡器的频率变化。

公开(公告)号：US20040046192A1

公开(公告)日：2004-03-11

申请号：US10454361

申请日：2003-06-04

Applicant: STMICROELECTRONICS S.A. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： Damien Lenoble ,  Isabelle Guilmeau

IPC: H01L029/76

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656

Abstract: Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.

Abstract translation: 用于制造晶体管的工艺包括产生源极和漏极延伸区域，其包括在半导体衬底上形成栅极区域，并且在晶体管的栅极的任一侧和距离晶体管的栅极的任意一侧离开半导体衬底中注入掺杂剂。 源极和漏极延伸区域的产生在于在栅极（GR）的侧壁上和半导体衬底的表面上形成中间层（Cl）。 该中间层由比二氧化硅致密的材料形成。 掺杂剂（IMP）的注入通过位于半导体衬底上的部分中间层进行。

公开(公告)号：US20040027098A1

公开(公告)日：2004-02-12

申请号：US10460039

申请日：2003-06-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Jerome Nebon

IPC: G05F001/613

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A control device is provided for a switching power supply having an output that supplies an output voltage. The switching power supply includes an inductor and two changeover switches for controlling coupling of the inductor. The control device includes a first capacitor for charging with continuous current from a 0 V voltage level, a second capacitor for discharging of the continuous current from a predetermined voltage level that is greater than the voltage level of a DC power supply, and a comparison circuit. The comparison circuit compares the output voltage of the switching power supply with voltage levels of the first and second capacitors and generates control signals for controlling the two changeover switches of the switching power supply. Also provided are switching power supplies having such control devices and a method for controlling a switching power supply.

Abstract translation: 为具有提供输出电压的输出的开关电源提供控制装置。 开关电源包括电感器和用于控制电感器耦合的两个转换开关。 控制装置包括用于从0V电压电平充电的连续电流的第一电容器，用于从大于DC电源的电压电平的预定电压电平放电连续电流的第二电容器，以及比较电路 。 比较电路将开关电源的输出电压与第一和第二电容器的电压电平进行比较，并产生用于控制开关电源的两个转换开关的控制信号。 还提供了具有这种控制装置的开关电源和用于控制开关电源的方法。