公开(公告)号：US20140331084A1

公开(公告)日：2014-11-06

申请号：US14358616

申请日：2012-03-16

Applicant: Junya Sawazaki ,  Naoki Ikawa ,  Kei Takeda

Inventor： Junya Sawazaki ,  Naoki Ikawa ,  Kei Takeda

IPC: G06F3/06 ,  G06F11/14 ,  G06F11/20

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0689 ,  G06F11/1402 ,  G06F11/2058 ,  G06F17/30911 ,  G06F2201/80 ,  G06F2201/845

Abstract: Information processing system for rapidly performing analysis of semistructured data while preserving fault-tolerance of data for a store request acquiring the number which has been stored of the same and data structures set beforehand, refer to data structure management information to determine a data store unit, instructs replica creation of the data with regard to the data stored in the data store unit in which any of the replicas have been stored, transmits an instruction, for performing a data operation, to a data structure operation unit, whereupon a processing unit, in accordance with the content of an analysis request, performs analysis processing by way of either data stored in any of the data storage units after a data structure operation or data which have not been subject to a data structure operation.

Abstract translation: 用于快速执行半结构化数据分析的信息处理系统，同时保存用于获取已经存储的数据的存储请求的数据的容错，以及预先设置的数据结构，参考数据结构管理信息来确定数据存储单元， 指示关于存储在其中存储任何副本的数据存储单元中的数据的数据的副本创建，用于执行数据操作的指令发送到数据结构操作单元，在该数据结构操作单元中，处理单元 根据分析请求的内容，通过在数据结构操作之后存储在任何数据存储单元中的数据或者未经过数据结构操作的数据执行分析处理。

公开(公告)号：US08826288B2

公开(公告)日：2014-09-02

申请号：US11109352

申请日：2005-04-19

Applicant: Andrew H. Barr ,  Ken G. Pomaranski

Inventor： Andrew H. Barr ,  Ken G. Pomaranski

IPC: G06F9/46

CPC classification number: G06F9/5044 ,  G06F9/5055 ,  G06F9/5066 ,  G06F11/1641 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/845 ,  G06F2209/5012

Abstract: A computer system provides for both lock-step and free-step processor modes, allowing for an effective tradeoff between performance and data integrity.

Abstract translation: 计算机系统提供锁步和自由步进处理器模式，允许在性能和数据完整性之间进行有效的折衷。

公开(公告)号：US08707094B2

公开(公告)日：2014-04-22

申请号：US13793267

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Mark J. Hickey ,  Adam J. Muff ,  Matthew R. Tubbs ,  Charles D. Wait

IPC: G06F11/16 ,  G06F11/00

CPC classification number: G06F11/0751 ,  G06F9/30185 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1641 ,  G06F2201/845

Abstract: A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.

Abstract translation: 电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。 对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行 。 因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供 对这种指令的无故障执行的更大保证。

公开(公告)号：US08375256B2

公开(公告)日：2013-02-12

申请号：US12467733

申请日：2009-05-18

Applicant: Wilhard von Wendorff ,  Detlev Leisengang

Inventor： Wilhard von Wendorff ,  Detlev Leisengang

IPC: G06F11/00

CPC classification number: G06F11/16 ,  G06F11/20 ,  G06F2201/845

Abstract: A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of data or signals between the functional units. At least one functional unit of the system is programmable and/or configurable such that it performs a particular function out of a number of different functions. The connection matrix is programmed and/or configured such that the functional units are connected with each other in a particular configuration out of a number of different configurations.

Abstract translation: 提供了一种用于处理具有多个功能单元的数据或信号的方法和系统，每个功能单元适于将一个或多个功能应用于数据或信号，并且经由用于交换的连接矩阵彼此连接 的功能单元之间的数据或信号。 系统的至少一个功能单元是可编程和/或可配置的，使得其执行多个不同功能的特定功能。 连接矩阵被编程和/或配置为使得功能单元在多个不同配置中的特定配置中彼此连接。

公开(公告)号：US20130019083A1

公开(公告)日：2013-01-17

申请号：US13179672

申请日：2011-07-11

Applicant: Harold W. Cain, III ,  David M. Daly ,  Kattamuri Ekanadham ,  Michael C. Huang ,  Jose E. Moreira ,  Mauricio J. Serrano

Inventor： Harold W. Cain, III ,  David M. Daly ,  Kattamuri Ekanadham ,  Michael C. Huang ,  Jose E. Moreira ,  Mauricio J. Serrano

IPC: G06F9/30

CPC classification number: G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F11/1492 ,  G06F11/1629 ,  G06F2201/845

Abstract: A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.

Abstract translation: 提供了用于一组指令的冗余执行的机制。 在该组指令中识别由第一处理器上的第一硬件线程执行的冗余执行开始（rbegin）指令。 rbegin指令之后的指令集在第一个硬件线程和第二个硬件线程上执行。 响应于所述第一处理器和所述第二处理器结束所述指令集的执行，响应于在第二推测存储器中匹配第二组高速缓存行的第一推测存储器中的第一组高速缓存行，并响应于第一集合 在与第二状态寄存器中的第二组寄存器状态匹配的第一状态寄存器中的寄存器状态被提交，从而将第一推测存储器中的脏线提交给架构状态的冗余事务状态。

公开(公告)号：US20120210162A1

公开(公告)日：2012-08-16

申请号：US13027932

申请日：2011-02-15

Applicant: Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

Inventor： Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

IPC: G06F11/08 ,  G06F11/00

CPC classification number: G06F11/1658 ,  G06F11/1064 ,  G06F11/1407 ,  G06F11/1641 ,  G06F11/1679 ,  G06F11/203 ,  G06F11/2043 ,  G06F2201/845

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, wherein the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.

Abstract translation: 用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。 提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。 每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设 设备等。存储器套件通过开关或总线连接到选择性配对设施。 每个选择性配对的处理器核心包括事务执行设施，其中所述系统被配置为使能处理器回滚到先前状态，并且重新初始化锁步执行，以便当所述选择性配对设施检测到不正确的执行时，从不正确的执行中恢复。

公开(公告)号：US20110235527A1

公开(公告)日：2011-09-29

申请号：US13133264

申请日：2009-11-25

Applicant: Rolf Buse ,  Benno Petersen ,  Jorg Wolfrum

Inventor： Rolf Buse ,  Benno Petersen ,  Jorg Wolfrum

IPC: H04L12/26

CPC classification number: G06F11/1633 ,  G06F11/165 ,  G06F2201/845

Abstract: The invention relates to a multichannel controller module for integrated modular avionics, having at least two channels, wherein, in each of the channels, at least one first interface, which is intended for communication with a control computer, a processor, at least one second interface, which is intended for communication with a peripheral, and a first memory, which is provided with an operating system, are connected in order to interchange data with one another, wherein a second memory is provided for selective storage of at least one application program for communication with the peripheral, wherein a selection means is provided, by means of which the application program is selectively assigned a first or a second mode of operation, wherein the first mode of operation is a redundant duplex mode of operation, in which both channels are used to execute the application program, and the two channels are in this case connected to one another via a data interchange and fault monitoring means, and wherein the second mode of operation is a non-redundant simplex mode of operation, in which only one of the two channels is used to .execute the application program, and the data interchange and fault monitoring means is in this case deactivated.

Abstract translation: 本发明涉及用于集成模块化航空电子设备的多通道控制器模块，其具有至少两个通道，其中在每个通道中至少一个第一接口用于与控制计算机通信处理器，至少一个第二通道 接口，其旨在用于与外围设备通信，以及设置有操作系统的第一存储器被连接以便彼此交换数据，其中提供第二存储器用于选择性地存储至少一个应用程序 用于与外围设备通信，其中提供选择装置，通过该选择装置，应用程序被选择性地分配第一或第二操作模式，其中第一操作模式是冗余双工操作模式，其中两个通道 用于执行应用程序，并且这两个通道在这种情况下通过数据交换和故障监视m相互连接 并且其中第二操作模式是非冗余单工模式，其中仅使用两个通道中的一个来执行应用程序，并且数据交换和故障监视装置在这种情况下被去激活。

公开(公告)号：US20110214125A1

公开(公告)日：2011-09-01

申请号：US13105041

申请日：2011-05-11

Applicant: Akira Bando ,  Shin Kokura ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hisao Nagayama ,  Naoya Mashiko ,  Masakazu Ishikawa ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Hiromichi Endoh ,  Tsutomu Yamada ,  Satoru Funaki

Inventor： Akira Bando ,  Shin Kokura ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hisao Nagayama ,  Naoya Mashiko ,  Masakazu Ishikawa ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Hiromichi Endoh ,  Tsutomu Yamada ,  Satoru Funaki

IPC: G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F2201/845

Abstract: An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results.

Abstract translation: 一种输入/输出控制装置，包括：响应于来自第二输入/输出单元的访问请求和来自第一输入/输出单元的访问请求来控制与多个处理器的计算有关的数据的输入/输出的单元 其要求比所述第二输入/输出单元更高的可靠性，并且命令多个处理器中的至少一个处理器执行与来自所述第一输入/输出单元的访问请求相关的计算，远离与所述第二输入/输出单元的访问请求有关的计算 在所述第一输入/输出单元发出访问请求的情况下，输入/输出单元，使得所述多个处理器进行相同的计算; 从所述多个处理器提供的所述第一输入/输出单元中比较所述计算结果与所述访问请求的单元; 以及允许基于所述比较结果输出与所述处理器的所述计算相关联的数据的单元。

公开(公告)号：US20110202737A1

公开(公告)日：2011-08-18

申请号：US13030192

申请日：2011-02-18

Applicant: Hideaki TAKAHASHI ,  Mana Tanaka ,  Hideyuki Tanaka

Inventor： Hideaki TAKAHASHI ,  Mana Tanaka ,  Hideyuki Tanaka

IPC: G06F12/16

CPC classification number: G06F11/201 ,  G06F11/2058 ,  G06F11/2071 ,  G06F11/2082 ,  G06F2201/815 ,  G06F2201/845 ,  G06F2201/855

Abstract: A storage apparatus includes: an associating unit that associates a first memory area in which data to be copied are stored and a second memory area of a destination storage apparatus to which the data are copied; a detecting unit that detects a start or an end of copying the data from the first memory area to the second memory area associated by the associating unit; and an access control unit that controls access to the first memory area and the second memory area based on a result of detection performed by the detecting unit.

Abstract translation: 存储装置包括：关联单元，其将要存储数据的第一存储区域与复制数据的目的地存储装置的第二存储区域相关联; 检测单元，其检测从所述第一存储器区域将数据复制到由所述关联单元关联的所述第二存储器区域的开始或结束; 以及访问控制单元，其基于由所述检测单元执行的检测结果来控制对所述第一存储区域和所述第二存储区域的访问。

公开(公告)号：US20110082970A1

公开(公告)日：2011-04-07

申请号：US12995317

申请日：2008-06-20

Applicant: Michael Rohleder ,  Gary Hay ,  Stephan Mueller ,  Manfred Thanner

Inventor： Michael Rohleder ,  Gary Hay ,  Stephan Mueller ,  Manfred Thanner

IPC: G06F12/02

CPC classification number: G06F11/1666 ,  G06F11/1629 ,  G06F11/167 ,  G06F2201/845 ,  G11C7/1075 ,  G11C29/74 ,  G11C2029/0411

Abstract: A system for distributing available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage.

Abstract translation: 一种用于分发可用存储器资源的系统，包括至少两个随机存取存储器（RAM）元件和RAM路由逻辑。 RAM路由逻辑包括用于动态地将可用存储器资源分配到提供冗余存储器存储器的第一存储器区域和提供非冗余存储器存储器的第二存储器区域的配置逻辑。