公开(公告)号：US20040016968A1

公开(公告)日：2004-01-29

申请号：US10409653

申请日：2003-04-08

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract translation: 提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与 渠道区域。 源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。 此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。 还提供了一种包括这种半导体器件的集成电路及其制造方法。

公开(公告)号：US20030174249A1

公开(公告)日：2003-09-18

申请号：US10356350

申请日：2003-01-30

Applicant: STMicroelectronics S.A.

Inventor： Lionel Grillo

IPC: H03M001/12

CPC classification number: H03M1/1295 ,  H04N5/18

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract translation: 用于视频电路输入级的校准装置包括模数转换器和由电源恒定放电并由充电电路借助于第一和第二充电电流再充电的输入电容器。 充电电路由接收对转换器的输出代码和钳位值之间的变化的估计的中央处理单元控制。

公开(公告)号：US20030160650A1

公开(公告)日：2003-08-28

申请号：US10351601

申请日：2003-01-24

Applicant: STMicroelectronics S.A.

Inventor： Pierre Rizzo

IPC: H03D001/00

CPC classification number: G06K19/0723 ,  H03D1/18 ,  H03K5/082

Abstract: A demodulator for an amplitude modulated alternating signal includes a peak detection circuit for extracting the reference modulating signal from the amplitude modulated alternating signal, and a first translation circuit for offsetting the level of the reference modulating signal by a value equal to the DC component to obtain an offset reference modulated signal. A comparison threshold generator circuit generates a comparison threshold to locate the start and the end of the modulation, and a comparator circuit compares the offset reference modulating signal with the comparison threshold for providing signals that cross the comparison threshold. An unregulated supply circuit provides a supply voltage to the different circuits.

Abstract translation: 用于幅度调制交替信号的解调器包括用于从调幅交替信号中提取参考调制信号的峰值检测电路和用于将参考调制信号的电平抵消等于DC分量的值的第一平移电路，以获得 偏移参考调制信号。 比较阈值发生器电路产生比较阈值以定位调制的开始和结束，并且比较器电路将偏移参考调制信号与比较阈值进行比较，以提供跨越比较阈值的信号。 不稳定的电源电路为不同的电路提供电源电压。

公开(公告)号：US20030119219A1

公开(公告)日：2003-06-26

申请号：US10308482

申请日：2002-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Alexis Farcy ,  Philippe Coronel ,  Pascal Ancey ,  Joaquin Torres

IPC: H01L021/00 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: B81C1/0023 ,  B29C2043/5825

Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Abstract translation: 集成电路的制造包括制造电子芯片的第一阶段和产生放置在芯片上方的至少一个辅助部件并产生覆盖辅助部件的保护盖的第二阶段。 制造芯片的第一阶段从第一半导体衬底实现，并且包括形成位于芯片的选定区域中并且出现在芯片的上表面处的空腔。 第二生产阶段包括从第二半导体衬底生产辅助部件，与第一半导体衬底分离，然后放置在由第二衬底支撑的辅助部件的空腔中，以及将第二衬底与上表面的相互粘合 的芯片位于腔外。 第二基板然后也形成保护盖。

公开(公告)号：US20030118129A1

公开(公告)日：2003-06-26

申请号：US10153000

申请日：2002-05-22

Applicant: STMICROELECTRONICS S.A.

Inventor： Marc Joisson ,  Luc Garcia ,  Sebastien Leveque

IPC: H03D003/00 ,  H04L027/14 ,  H04B001/16

CPC classification number: H04L27/1563

Abstract: A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

Abstract translation: 表示数字信号的频率调制信号的接收机包括降频变频单元或频率转换单元，以降低频率调制信号的频率，以及数字解调器，以从低频信号再生数字信号。 接收器还包括一个计数器电路，用于在降频信号的周期期间确定来自频率转换单元的参考信号的周期数。 数字解调器包括计算机单元，用于根据参考信号的周期数来计算降频信号的周期。

公开(公告)号：US20030102577A1

公开(公告)日：2003-06-05

申请号：US10315870

申请日：2002-12-09

Applicant: STMicroelectronics S.A.

Inventor： Yvon Gris

IPC: H01L027/088

CPC classification number: H01L29/66242 ,  H01L29/66272

Abstract: A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

公开(公告)号：US20030095453A1

公开(公告)日：2003-05-22

申请号：US10299965

申请日：2002-11-19

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.

Abstract translation: 本发明涉及包括读阶段（RDST），参考级（RFST）和包括PMOS和NMOS型晶体管的差分输出级的读放大器（SA2）。 根据本发明，差分级（DIFST2）的晶体管仅包括串联的一个PMOS晶体管（TP3）和一个NMOS晶体管（TN3），PMOS晶体管（TP3）的栅极连接到读取级的一个节点 （RDST），其栅极连接到参考级（RFST）的一个节点的NMOS晶体管（TN3），差分级的PMOS和NMOS晶体管的中点形成读取的数据输出节点（DATAOUT） 放大器 根据本发明的读取放大器具有短的读取时间和低的电力消耗的组合优点。 应用于EPROM，EEPROM和FLASH型非易失性存储器。

公开(公告)号：US20030090936A1

公开(公告)日：2003-05-15

申请号：US10277183

申请日：2002-10-21

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C016/04

CPC classification number: G11C16/20

Abstract: An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.

Abstract translation: 电可擦除可编程存储器（EEPROM）包括存储器阵列，存储器阵列包含连接到排列成行的字线和以列排列的位线的存储器单元。 存储器阵列包括用于存储第一类型的特殊位的第一特殊区域和用于存储第二类型的特殊位的第二特殊区域。 第一特殊区域包括连接到第一字线的第一行存储器单元，其中N1个存储器单元连接到存储器阵列的确定列的N1位线。 第二特殊区域包括连接到第二字线的第二行存储单元，其中N2个存储单元连接到所确定列的N2个其它位线。 N1位线未连接到第二行存储单元，N2位线未连接到第一行存储单元。

公开(公告)号：US20030071687A1

公开(公告)日：2003-04-17

申请号：US10245842

申请日：2002-09-17

Applicant: STMicroelectronics S.A.

Inventor： Marius Reffay ,  Michel Barou

IPC: H03F003/18

CPC classification number: H03F1/308 ,  H03F1/3217

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract translation: AB类放大器电路包括互补输出级和用于偏置输出级的偏置电路。 互补输出级包括P型MOS晶体管和N型MOS晶体管，偏置电路包括双极晶体管。 双极晶体管的发射极和集电极分别连接到P型和N型MOS晶体管的栅极。 双极晶体管被偏置用于控制P型和N型MOS晶体管的各个栅极之间的偏置电压。

公开(公告)号：US20030063498A1

公开(公告)日：2003-04-03

申请号：US10228164

申请日：2002-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。