公开(公告)号：US5959571A

公开(公告)日：1999-09-28

申请号：US981054

申请日：1997-12-11

Applicant: Yasushi Aoyagi ,  Toshihide Fukuchi ,  Kiyoshi Inoue ,  Ryuji Kohno

Inventor： Yasushi Aoyagi ,  Toshihide Fukuchi ,  Kiyoshi Inoue ,  Ryuji Kohno

IPC: G01S7/02 ,  G01S13/32 ,  G01S13/42 ,  G01S13/93

CPC classification number: G01S13/325 ,  G01S13/42 ,  G01S2013/9375

Abstract: A radar device transmits an electric wave whose band is spread by a PN code, receives a reflected wave of the electric wave from an object 10, detects correlation between a received signal and a PN code which is delayed, and thereby detects the object. A receiving part 18 connects three receiving antennas 16a.about.16c sequentially one by one, thereby to receive a reflected wave from an object. The three receiving antennas are arranged having their directions so staggered that their antenna beam patterns partly overlap with each other. A correlation detection circuit 19 detects such a slide width that a value of correlation between a received signal received by each of the antennas and the PN code exceeds a predetermined threshold. An operation part 12 obtains an azimuth of an object based on the detected slide width and beam pattern characteristics of the antennas.

Abstract translation: PCT No.PCT / JP97 / 10372 Sec。 371 1997年12月11日第 102（e）日期1997年12月11日PCT 1997年4月22日提交PCT公布。 公开号WO97 / 40400 PCT 日期1997年10月30日雷达装置发送带宽由PN码扩展的电波，从对象10接收电波的反射波，检测接收信号与被延迟的PN码之间的相关性，从而 检测物体。 接收部分18依次连接三个接收天线16a差分16c，从而接收来自物体的反射波。 三个接收天线被布置成具有如此交错的方向，使得它们的天线波束图案彼此部分重叠。 相关检测电路19检测由每个天线接收的接收信号与PN码之间的相关值超过预定阈值的滑动宽度。 操作部分12基于检测到的天线的滑动宽度和波束图案特性来获得对象的方位角。

公开(公告)号：US5910010A

公开(公告)日：1999-06-08

申请号：US732215

申请日：1997-02-18

Applicant: Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

Inventor： Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

IPC: H01L21/56 ,  H01L21/98 ,  H01L23/495 ,  H01L25/065 ,  H01L21/52 ,  H01L21/58 ,  H01L21/60

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract translation: PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号 日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部 每一帧。 然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。 然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。 然后将树脂包装从模具部件中释放出来。

公开(公告)号：US5889916A

公开(公告)日：1999-03-30

申请号：US786084

申请日：1997-01-17

Applicant: Katsumi Kimura ,  Kenji Maekawa ,  Shigeru Kato ,  Masataka Mukai ,  Masao Naito ,  Kiyoshi Inoue ,  Takeo Nishijima

Inventor： Katsumi Kimura ,  Kenji Maekawa ,  Shigeru Kato ,  Masataka Mukai ,  Masao Naito ,  Kiyoshi Inoue ,  Takeo Nishijima

IPC: H04N5/765 ,  G11B27/00 ,  G11B27/032 ,  G11B27/11 ,  G11B27/32 ,  H04N5/77 ,  H04N5/781 ,  H04N5/7826 ,  H04N5/907 ,  H04N9/804 ,  H04N5/93 ,  H04N5/91

CPC classification number: G11B27/326 ,  G11B27/032 ,  G11B27/11 ,  H04N5/772 ,  G11B2220/655 ,  G11B2220/90 ,  H04N9/8047

Abstract: A video data recording apparatus for recording video data using a tape-like recording medium accommodated in a cassette provided with a semiconductor memory by which it is possible to suitably determine the cuts and make effective use of the semiconductor memory to enable efficient editing. The user can mark the recorded video data with the desired starting position and ending position of the video data. The marked cuts are used to extract the index picture and, at the same time, the recording positions of the cuts and an index picture on the tape recording medium are recorded in the semiconductor memory.

Abstract translation: 一种用于使用容纳在具有半导体存储器的盒中的带状记录介质来记录视频数据的视频数据记录装置，通过该记录介质可以适当地确定切割并有效利用半导体存储器以实现有效的编辑。 用户可以利用期望的视频数据的起始位置和结束位置来标记记录的视频数据。 标记的切口用于提取索引图像，并且同时将切割的记录位置和带记录介质上的索引图像记录在半导体存储器中。

公开(公告)号：US5724041A

公开(公告)日：1998-03-03

申请号：US561985

申请日：1995-11-22

Applicant: Kiyoshi Inoue ,  Haruhiko Ishizu ,  Ryuji Kohno

Inventor： Kiyoshi Inoue ,  Haruhiko Ishizu ,  Ryuji Kohno

IPC: G01S7/02 ,  G01S7/285 ,  G01S13/28 ,  G01S13/34 ,  G01S13/58 ,  G01S13/93

CPC classification number: G01S13/931 ,  G01S13/346 ,  G01S13/584 ,  G01S7/285 ,  G01S13/284 ,  G01S2013/9375

Abstract: A radar device transmits by a transmitting part a wave whose band is spread by a PN code from a PN generator, receives at a receiving part a reflected wave from an object based on the wave and detects the object by detecting correlation between the received signal and the PN code. In this radar device, the received signal which is spread to a wide range is converted to a low-frequency band which is easy to be measured by a down converter so that a signal is generated when correlation is made by a delay of the PN code from a delay circuit, and generates a pulse signal through waveform shaping of the signal to detect the object and to measure its relative speed and distance at a processing part according to the pulse signal and the delay time.

Abstract translation: 雷达装置由发射部分发送波段，其波段由PN发生器通过PN码扩展，在接收部分接收基于波的对象的反射波，并通过检测接收信号和 PN码。 在该雷达装置中，扩展到宽范围的接收信号被转换为易于由下变频器测量的低频带，使得当通过PN码的延迟进行相关时产生信号 并且通过信号的波形整形产生脉冲信号，以检测物体，并根据脉冲信号和延迟时间测量处理部分的相对速度和距离。

公开(公告)号：US5715190A

公开(公告)日：1998-02-03

申请号：US658081

申请日：1996-06-04

Applicant: Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

Inventor： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105

CPC classification number: G11C11/22

Abstract: A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

Abstract translation: 存储矩阵，其包括以矩阵排列的每个由铁电电容器和地址选择MOSFET构成的存储单元，其被划分为多个存储块。 每个存储块设置有模式存储电路，其针对每个存储块以一对应的对应关系存储DRAM模式（易失性模式）或NV模式（非易失性模式），并且利用刷新操作计数电路 每个内存块对连续执行刷新操作的次数进行计数。 在第n次刷新操作（其中n是预定次数）的情况下，进行存储器访问以将铁电电容器的板电压从一个电压临时地改变为另一个电压，同时模式存储电路从 DRAM模式为NV模式。 当执行对存储器块中的存储单元的读取或写入操作时，模式存储电路从NV模式改变为DRAM模式。 根据模式存储电路中存储的信息，对于被设置为NV模式的存储器块，省略刷新操作。

公开(公告)号：US5691952A

公开(公告)日：1997-11-25

申请号：US590608

申请日：1996-01-24

Applicant: Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

Inventor： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C13/00

CPC classification number: G11C29/80 ,  G11C29/74 ,  G11C29/808 ,  G11C29/832

Abstract: Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

Abstract translation: 第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障 在记忆垫单位。 电源基本上被切断供给故障存储器垫。

公开(公告)号：US5510043A

公开(公告)日：1996-04-23

申请号：US243821

申请日：1994-05-17

Applicant: Kiyoshi Inoue

Inventor： Kiyoshi Inoue

IPC: C10M135/30 ,  C10M135/02

CPC classification number: C10M135/30 ,  C10M2219/087 ,  C10M2219/088 ,  C10M2219/089 ,  C10N2240/02 ,  C10N2240/08 ,  C10N2240/10 ,  C10N2240/101 ,  C10N2240/102 ,  C10N2240/103 ,  C10N2240/104 ,  C10N2240/106

Abstract: A lubricating oil additive comprising an alkaline earth metal salt of a sulfurized monoalkylcatechol as a main component represented by the following general formula (I): ##STR1## wherein Me represents an alkaline earth metal, R.sup.1 and R.sup.2 represent each an alkyl group having 14 to 30 carbon atoms, m is a number of from 1 to 2, which provides a lubricating oil additive excellent in anti-oxidant, friction-reducing and anti-abrasive properties at high temperature.

Abstract translation: 1.一种润滑油添加剂，其特征在于，含有以下通式（I）表示的硫化单烷基邻苯二酚的碱土金属盐作为主要成分：其中Me表示碱土金属，R1和R2分别表示烷基 具有14至30个碳原子，m为1至2的数量，其提供在高温下抗氧化剂，摩擦降低和抗磨损性能优异的润滑油添加剂。

公开(公告)号：US5380508A

公开(公告)日：1995-01-10

申请号：US112091

申请日：1993-08-26

Applicant: Kiyoshi Inoue

Inventor： Kiyoshi Inoue

IPC: C07F5/04 ,  C10M159/22 ,  C01B35/12

CPC classification number: C07F5/04 ,  C10M159/22 ,  C10M2207/028 ,  C10M2207/262 ,  C10N2270/00

Abstract: This invention provides a calcium borate overbased salicylate as an additive for petroleum products which has been overbased with meta-calcium borate having a particle diameter of not larger than 200 angstrom, said meta-calcium borate being prepared by two steps of (1) reacting a mixture of (A) 100 parts by weight of oil-soluble calcium salicylate, (B) 10 to 200 parts by weight, of calcium hydroxide or oxide, (C) 1.5 to 2.5 moles, per mole of said component B, of orthoboric acid, (D) 60 to 200 parts by weight of an alkanol of 1 to 4 carbon atoms, (E) 1 to 40 parts by weight of water and (F) 40 to 1000 parts by weight of a diluent which is a nonpolar organic solvent having a boiling point of 60.degree. C. or higher, at a temperature of from 20.degree. to 120.degree. C. for 2 to 8 hours, and then (2) heating the reaction mixture to 100.degree. to 200.degree. C. thereby to remove the water therefrom by distillation.

Abstract translation: 本发明提供了一种硼酸钙高碱性水杨酸盐作为石油产品的添加剂，该添加剂已经用粒径不大于200埃的硼酸钙硼酸盐进行过碱性处理，所述硼酸钙是由以下两个步骤制备的：（1）使 （A）100重量份油溶性水杨酸钙，（B）10至200重量份氢氧化钙或氧化物，（C）1.5至2.5摩尔/摩尔所述组分B的原硼酸 ，（D）60〜200重量份的碳原子数1〜4的链烷醇，（E）1〜40重量份的水和（F）40〜1000重量份作为非极性有机溶剂的稀释剂 沸点为60℃以上，温度为20〜120℃2〜8小时后，（2）将反应混合物加热至100〜200℃，除去 通过蒸馏得到的水。

公开(公告)号：US5322574A

公开(公告)日：1994-06-21

申请号：US743223

申请日：1991-08-09

Applicant: Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

Inventor： Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

IPC: C22C9/00 ,  C22F1/00 ,  C22F1/02 ,  C22F1/08 ,  H01L23/48 ,  H01L23/495

CPC classification number: H01L23/49579 ,  C22F1/02 ,  C22F1/08 ,  H01L2924/0002

Abstract: The present invention provides a new copper alloy containing silver from 4 to 32 at. %, which is useful for a magnet conductor, an IC lead frame, etc., having simultaneously a high strength and a high conductivity, manufactured by blending from 4 to 32 at. % silver into copper, casting, rapidly cooling and cold-working wherein the cold-working step includes a hot working treatment at a reduction rate of 40% to 70% at temperatures of from 300.degree. to 500.degree. C.

Abstract translation: 本发明提供一种含有4〜32at银的新型铜合金。 ％，其对于具有高强度和高导电性的磁体导体，IC引线框架等是有用的，通过混合4至32at制造。 ％银成铜，铸造，快速冷却和冷加工，其中冷加工步骤包括在300℃至500℃的温度下以40％至70％的还原率进行的热加工处理。

公开(公告)号：US5307340A

公开(公告)日：1994-04-26

申请号：US815922

申请日：1991-12-30

Applicant: Kiyoshi Inoue ,  Kyosuke Hashimoto ,  Yutaka Matsuda ,  Shoji Hara ,  Kunio Odaka ,  Seiji Hirano ,  Osamu Michihira ,  Yoshikazu Nobutoki

Inventor： Kiyoshi Inoue ,  Kyosuke Hashimoto ,  Yutaka Matsuda ,  Shoji Hara ,  Kunio Odaka ,  Seiji Hirano ,  Osamu Michihira ,  Yoshikazu Nobutoki

IPC: B60R16/02 ,  B60R16/03 ,  H04L12/413 ,  H04J3/14

CPC classification number: H04L12/40182 ,  H04L12/4135 ,  B60R16/0315

Abstract: A multipath transmission system according to the present invention comprises a plurality of multiplex nodes connected to two multiplex buses. Each of the multiplex nodes is assigned to a specific apparatus, and includes a communication control circuit (LSI) for fetching multiplex signals from the apparatus and transmitting the multiplex signals to the multiplex buses. One multiplex node, out of the plurality of multiplex nodes, includes communication control circuits driver/receiver circuits, and troubleshooting driver/receiver circuits, which are connected to the multiplex buses and used for signal transfer between the buses, and a microprocessor for troubleshooting the multiplex buses and the multiplex nodes. The multiplex node relays a failure signal, corresponding to the result of troubleshooting, to the other network which suffers no trouble.

Abstract translation: 根据本发明的多径传输系统包括连接到两个多路复用总线的多个复用节点。 每个多路复用节点被分配给特定装置，并且包括用于从装置取出多路复用信号并将多路复用信号发送到多路复用总线的通信控制电路（LSI）。 在多个多路复用节点中的一个多路复用节点包括连接到多路复用总线并用于总线之间的信号传输的通信控制电路驱动器/接收器电路和故障排除驱动器/接收器电路以及用于故障排除的微处理器 多路复用总线和多路复用节点。 多路复用节点将与故障诊断结果相对应的故障信号中继到没有故障的其他网络。