公开(公告)号：WO2010028836A1

公开(公告)日：2010-03-18

申请号：PCT/EP2009/006594

申请日：2009-09-10

Applicant: STMICROELECTRONICS S.R.L. ,  COZZI, Pier, Giorgio ,  ZOLI, Luca ,  BRAMANTI, Alessandro, Paolo

Inventor： COZZI, Pier, Giorgio ,  ZOLI, Luca ,  BRAMANTI, Alessandro, Paolo

IPC: C07F17/02 ,  G06N99/00

CPC classification number: G06N99/002 ,  B82Y10/00 ,  C07F17/02

Abstract: Bistable carbazole compounds of formula (I) are described, wherein M is Fe, Co, Ru or Os, preferably Fe, useful as basic functional units for computing systems based on the QCA (Quantum Cellular Automata) paradigm; a process for their preparation is also described.

Abstract translation: 描述了式（I）的双稳态咔唑化合物，其中M是Fe，Co，Ru或Os，优选Fe，可用作基于QCA（Quantum Cellular Automata）范式的计算系统的基本功能单元; 还描述了其制备方法。

公开(公告)号：WO2008023395A1

公开(公告)日：2008-02-28

申请号：PCT/IT2006/000628

申请日：2006-08-25

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关容量电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有输出电压（OUT），该输出电压取决于可由源极（1）提供的输入电压（VIN） ）到缓冲装置; - 可以分别在其连接的第一和第二状态之间切换到电源和电容缓冲器以将输入电压传送到输出端的电容性开关部件（C SUB） 所述部件设置有具有相关联的杂散能力（C P1）的端子（N2）。 该装置还包括一个充电和放电装置（SW＆lt; CPIR＆gt;，＆lt;＆gt; G＆gt;），其被配置为在占用第二个参考电压之前对参考电压（REFM）预充电杂散容量 条件，并且在摄取第一个条件之前预先排出杂散容量。

公开(公告)号：WO2007148358A1

公开(公告)日：2007-12-27

申请号：PCT/IT2006/000485

申请日：2006-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  MAGNI, Pierangelo ,  BRIOSCHI, Roberto

Inventor： MAGNI, Pierangelo ,  BRIOSCHI, Roberto

IPC: B01L3/00

CPC classification number: B01L3/502707 ,  B01L2200/027 ,  B01L2200/10 ,  B01L2300/043 ,  B01L2300/0609 ,  B01L2300/0867 ,  B01L2300/123 ,  B01L2300/1805 ,  B01L2400/0481 ,  B01L2400/0622 ,  B01L2400/0638 ,  B01L2400/0644 ,  Y10T436/25 ,  Y10T436/2575

Abstract: In a microfluidic assembly (20), a microfluidic device (I1) is provided with a body (4) in which at least a first inlet (7) for loading a fluid to analyse and a buried area (8) in fluidic communication with the first inlet (7) are defined. An analysis chamber (10') is in fluidic communication with the buried area (8) and an interface cover (23) is coupled in a fluid-tight manner above the microfluidic device (I1) . The interface cover (23) is provided with a sealing portion (35) in correspondence to the analysis chamber (10')/ adapted to assume a first configuration, at rest, in which it leaves the analysis chamber (10') open, and a second configuration, as a consequence of a stress, in which it closes in a fluid-tight manner the same analysis chamber.

Abstract translation: 在微流体组件（20）中，微流体装置（I1）设置有主体（4），其中至少第一入口（7）用于装载待分析的流体和与该流体相通的埋入区域（8） 定义第一入口（7）。 分析室（10'）与掩埋区域（8）流体连通，并且界面盖（23）以流体密封的方式联接在微流体装置（I1）上方。 接口盖（23）设置有与分析室（10'）对应的适于呈现静止状态的第一配置（其离开分析室10'）的密封部分（35），以及 作为应力的结果的第二构造，其以不流体密封的方式封闭相同的分析室。

公开(公告)号：WO2007113878A1

公开(公告)日：2007-10-11

申请号：PCT/IT2006/000229

申请日：2006-04-06

Applicant: STMICROELECTRONICS S.R.L. ,  RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

Inventor： RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

IPC: G11B9/00

CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

Abstract translation: 这里描述的是用于制造用于存储介质（4）的相互作用结构（6）的方法，其设想形成具有第二导电区域（22）的第一相互作用头部（7），所述第一导电区域具有次光刻尺寸较小（Wi） 。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁（15b）的第一限定区域（15）; 在所述侧壁（15b）上沉积具有基本上与所述亚光刻较小尺寸（Wi）匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（Wi）在1至50nm之间，优选20nm。

公开(公告)号：WO2007091280A1

公开(公告)日：2007-08-16

申请号：PCT/IT2006/000061

申请日：2006-02-06

Applicant: STMICROELECTRONICS S.R.L. ,  FERRARA, Francesco ,  POMPA, Pier, Paolo ,  RINALDI, Ross

Inventor： FERRARA, Francesco ,  POMPA, Pier, Paolo ,  RINALDI, Ross

IPC: G01N21/64 ,  C12Q1/68

CPC classification number: G01N21/645 ,  C12Q1/6825 ,  G01N21/6445 ,  C12Q2561/119 ,  C12Q2523/313

Abstract: An optical apparatus for the inspection of nucleic acid probes includes: a holder (22) for housing a chip (1) for analysis of nucleic acids, containing nucleic acid probes (12, 12' ); a light (24), for supplying an excitation radiation (WE) to the holder (22); and an optical sensor (25) for detecting images (IMG) of the nucleic acid probes (12, 12'), when a chip (1) is housed in the holder (22). The light source (24) is configured for polarizing the excitation radiation (WE) according to a excitation polarization direction (DE). Furthermore, the apparatus is provided with a sensing polarizing filter (27), which is arranged so as to intercept a reflected portion (WR) of the excitation radiation (WE), directed towards the optical sensor (25). The sensing polarizing filter (27) has a direction of the sensing polarization (D3) transverse to the excitation polarization direction (DE).

Abstract translation: 用于检查核酸探针的光学装置包括：用于容纳用于核酸分析的芯片（1）的保持器（22），其包含核酸探针（12,12'）; 用于向所述保持器（22）提供激发辐射（WE）的光（24）; 以及当芯片（1）容纳在保持器（22）中时用于检测核酸探针（12,12'）的图像（IMG）的光学传感器（25）。 光源（24）被配置为根据激发偏振方向（DE）使激发辐射（WE）偏振。 此外，该装置设置有感测偏振滤光器（27），该感测偏振滤光器被布置成拦截朝向光学传感器（25）的激发辐射（WE）的反射部分（WR）。 感测偏振滤光器（27）具有横向于激发偏振方向（DE）的感测偏振方向（D3）。

公开(公告)号：WO2007006507A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006675

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a semiconductor substrate (10) with wide band gap comprising a first superficial semiconductor layer (11) with wide band gap of a first type of conductivity, comprising the steps of: forming trench regions (13) in the first superficial semiconductor layer (H), filling in said trench regions (13) by means of a second semiconductor layer (14) with wide band gap of a second type of conductivity, so as to form semiconductor portions (15) of the second type of conductivity contained in the first superficial semiconductor layer (11), carrying out at least one ion implantation of a first type of dopant in the semiconductor portions (15) for forming respective implanted body regions (19) of said second type of conductivity, carrying out at least one ion implantation of a second type of dopant in each of the implanted body regions (19) for forming at least one implanted source region (23) of the first type of conductivity inside the implanted body regions (19), carrying out an activation thermal process of the first and second type of dopant with low thermal budget suitable to complete said formation of the implanted body and source regions (19, 23).

Abstract translation: 一种用于制造具有宽带隙的半导体衬底（10）上的垂直功率MOS晶体管的方法，包括具有第一类型导电性的宽带隙的第一表面半导体层（11），包括以下步骤：形成沟槽区域（13） 在第一表面半导体层（H）中，通过具有第二导电类型的宽带隙的第二半导体层（14）填充所述沟槽区域（13），以形成第二半导体层 在第一表面半导体层（11）中包含的第二类导电体，在半导体部分（15）中进行至少一种第一类型掺杂剂的离子注入，用于形成所述第二导电类型的各个植入体区域（19） 在每个植入体区域（19）中进行至少一个第二类型掺杂剂的离子注入，用于在im内形成至少一个第一类型的电导率的注入源区（23） 植入体区域（19），以适合于完成植入体和源区（19,23）的所述形成的低热预算进行第一和第二类型掺杂剂的活化热处理。

公开(公告)号：WO2007006503A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006671

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).

Abstract translation: 一种用于制造功率电子器件（30）的方法，包括以下步骤：形成第一类型的导电性的第一半导体层（21），其形成至少第二类型的电导率值的第二半导体层（22），其在第一半导体 在所述至少第二半导体层（22）中形成所述第一类型的导电形成的第一多个注入区域（D1），在所述至少第二半导体层（22）之上，表面（21），表面 在所述表面半导体层（26）中形成所述第一导电类型的半导体层（26），所述半导体层（26）在所述第二导电类型的主体区域（40）中形成，所述主体区域（40）与半导体层 从所述多个所述至少第二注入区域（D1）中，进行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续的注入区域（D）。

公开(公告)号：WO2006120221A1

公开(公告)日：2006-11-16

申请号：PCT/EP2006/062224

申请日：2006-05-10

Applicant: STMicroelectronics S.r.l. ,  SCURATI, Mario Giovanni

Inventor： SCURATI, Mario Giovanni

IPC: B81C1/00 ,  B01L3/00 ,  F04B19/00

CPC classification number: B01L3/50273 ,  B01L3/502707 ,  B01L3/502738 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/0825 ,  B01L2300/087 ,  B01L2300/1827 ,  B01L2400/049 ,  B01L2400/0677 ,  Y10T29/49826 ,  Y10T137/0396 ,  Y10T137/2224

Abstract: A microfluidic device for nucleic acid analysis includes a monolithic semiconductor body (13), a microfluidic circuit (10), at least partially accommodated in the monolithic semiconductor body (13), and a micropump (11). The microfluidic circuit (10) includes a sample preparation channel (18) formed on the monolithic semiconductor body (13) and at least one microfluidic channel (20, 22) buried in the monolithic semiconductor body (13). The micropump (11), includes a plurality of sealed chambers (40) provided with respective openable sealing elements (41) and having a first pressure therein that is different from a second pressure in the microfluidic circuit (10). In addition, the micropump (11) and the microfluidic circuit (10) are configured so that opening the openable sealing elements (41) provides fluidic coupling between the respective chambers (40) and the microfluidic circuit (10). The openable sealing elements (41) are integrated in the monolithic semiconductor body (13).

Abstract translation: 用于核酸分析的微流体装置包括至少部分地容纳在单片半导体本体（13）中的单片半导体本体（13），微流体电路（10）和微型泵（11）。 微流体回路（10）包括形成在单片半导体本体（13）上的样品制备通道（18）和埋在单片半导体本体（13）中的至少一个微流体通道（20,22）。 微型泵（11）包括多个密封室（40），其设置有相应的可开启的密封元件（41），并且其中具有与微流体回路（10）中的第二压力不同的第一压力。 此外，微型泵（11）和微流体回路（10）构造成使得可打开的密封元件（41）的打开在各个腔室（40）和微流体回路（10）之间提供流体耦合。 可打开的密封元件（41）集成在单片半导体本体（13）中。

公开(公告)号：WO2006106556A1

公开(公告)日：2006-10-12

申请号：PCT/IT2006/000223

申请日：2006-04-04

Applicant: STMICROELECTRONICS S.R.L. ,  ZAPPA, Diego ,  FAZIO, Giuseppe ,  COLOMBO, Roberto

Inventor： ZAPPA, Diego ,  FAZIO, Giuseppe ,  COLOMBO, Roberto

IPC: G01N21/73 ,  H01J37/32

CPC classification number: H01J37/32972 ,  G01N21/73 ,  H01J37/32935

Abstract: A method for facilitating the determination of the end point of a dry plasma etching process of a material, is proposed. The method includes performing an analysis of the whole spectrum of a radiation generated during the plasma etching process of the material, the analysis comprising evaluating the time trend of a plurality of spectral components of the radiation, each spectral component indicating the time trend of the radiation intensity of a corresponding wavelengths interval of the radiation. The method further includes, on the basis of such analysis, selecting at least one of the spectral components, wherein the at least one spectral component has a time trend indicative of the evolution of the etching process of the material. The performing of the spectral analysis comprises performing a statistical analysis of the time trend of the whole spectrum of the radiation and, on the basis of the results of the statistical analysis, selecting the at least one spectral component.

Abstract translation: 提出了一种便于确定材料的干等离子体蚀刻工艺的终点的方法。 该方法包括对材料的等离子体蚀刻过程中产生的辐射的整个光谱进行分析，该分析包括评估辐射的多个光谱分量的时间趋势，每个光谱分量指示辐射的时间趋势 辐射的相应波长间隔的强度。 该方法还包括在这种分析的基础上，选择光谱分量中的至少一个，其中至少一个光谱分量具有指示材料的蚀刻过程演变的时间趋势。 光谱分析的执行包括对整个辐射光谱的时间趋势进行统计分析，并且基于统计分析的结果，选择至少一个光谱分量。

公开(公告)号：WO2006090417A1

公开(公告)日：2006-08-31

申请号：PCT/IT2005/000110

申请日：2005-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

Inventor： MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

IPC: H01L21/768 ,  B82B1/00

CPC classification number: B82Y10/00 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for realising a nanometric circuit architecture (2) in a semiconductor device comprising the steps of: a) realising a plurality of active areas (1) on a substrate (A) of the semiconductor device; b) realising on the substrate (A) a seed layer (4) of a first material; c) realising a mask-spacer (5) of a second material on the seed layer (4) in a region (A’) of the substrate (A) comprised between said active areas (1), said mask-spacer (5) being realised by MSPT and having at least one end portion (5) extending over the region (A’); d) realising at least one mask (6) overlapping the mask-spacer (5) and extending in a substantially perpendicular direction thereto (5); e) selectively removing the seed layer (4) being exposed on the substrate (A); f) selectively removing the mask (6) and the mask-spacer (5) obtaining a seed-spacer (7; 70) comprising a linear portion (7a) extending in that region (A’) and connected to at least one portion (7b) being substantially orthogonal thereto; g) eventually realising at least one insulating spacer (8) from said seed-spacer (7; 70) through the MSPT, that at least one insulating spacer (8) reproducing at least part of the profile of said seed-spacer (7; 70); h) realising at least one nano-wire (3; 13; 23) of conductive material from the seed-spacer (7, 70) or from the at least one insulating spacer (8) through the MSPT, the at least one nano-wire (3; 13; 23; 33) comprising a first portion (3a; 13a) at least partially extending in said region (A’) and at least one second portion (3b; 13b) in contact with a respective active area (1), the second portion (3b; 13b) being substantially orthogonal to the first portion (3a; 13a).

Abstract translation: 本发明涉及一种在半导体器件中实现纳米电路结构（2）的方法，包括以下步骤：a）在半导体器件的衬底（A）上实现多个有源区（1）; b）在基板（A）上实现第一材料的种子层（4）; c）在所述有源区（1），所述掩模间隔物（5）之间的衬底（A）的区域（A'）中实现种子层（4）上的第二材料的掩模间隔物（5） 通过MSPT实现并且具有在区域（A'）上延伸的至少一个端部（5）; d）实现与所述掩模间隔件（5）重叠并沿基本垂直的方向（5）延伸的至少一个掩模（6）; e）选择性地去除暴露在基底（A）上的种子层（4）; f）选择性地去除掩模（6）和掩模间隔物（5），获得包括在该区域（A'）中延伸并连接到至少一个部分（A'）的直线部分（7a）的种子间隔物（7; 70） 7b）基本上与其正交; g）最终通过MSPT从所述种子间隔物（7; 70）中实现至少一个绝缘间隔物（8），至少一个绝缘间隔物（8）再现至少部分所述种子间隔物（7; 70）; h）从所述种子间隔物（7,70）或通过所述MSPT从所述至少一个绝缘间隔物（8）实现至少一个导电材料的纳米线（3; 13; 23），所述至少一个纳米线 包括在所述区域（A'）中至少部分地延伸的第一部分（3a; 13a）和与相应的有效区域（1）接触的至少一个第二部分（3b; 13b）的导线（3; 13; 23; 33） ），所述第二部分（3b; 13b）基本上与所述第一部分（3a; 13a）正交。