中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

265 records (took 0.018 seconds)

    병렬 스크램블링 회로
    256.
    发明授权
    병렬 스크램블링 회로 失效
    多路复用传输系统中的并联电路

    公开(公告)号：KR1019920007094B1

    公开(公告)日：1992-08-24

    申请号：KR1019890020555

    申请日：1989-12-30

    Applicant: 한국전자통신연구원 ,  주식회사 케이티

    Inventor： 엄두섭 ,  김홍주 ,  김재근

    IPC: H04K1/00

    Abstract: The parallel scrambling circuit realizes multiple transmission system by processing transmission signal with high speed by 8-bit units. The circuit includes a series to parallel converter (21) for converting serial input data to 8-bit parallel data, a first latch (22) for latching the 8-bit parallel data, a PN sequence generator (23) for generating 7 PN sequences a decimation sequence generator (24) for generating 8 decimation sequences related to 8-bit parallel data, a scrambling output generator (25) for scrambling the 8-bit parallel data, a second latch (26) for latching the scrambled 8-bit parallel data, and a parallel to series converter (27) for converting 8-bit scrambled data to serial data.

    Abstract translation: 并行加扰电路通过8位单位高速处理传输信号实现多传输系统。 该电路包括用于将串行输入数据转换为8位并行数据的串并联转换器（21），用于锁存8位并行数据的第一锁存器（22），用于产生7个PN序列的PN序列发生器（23） 用于产生与8位并行数据相关的8个抽取序列的抽取序列生成器（24），用于对8位并行数据进行加扰的加扰输出发生器（25），用于锁存8位并行数据的第二锁存器 数据和并行到串行转换器（27），用于将8位加扰数据转换为串行数据。

Patent Agency Ranking