公开(公告)号：US10169245B2

公开(公告)日：2019-01-01

申请号：US15784625

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/1027 ,  G06F12/0862 ,  G06F13/16 ,  G06F9/00

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US10146681B2

公开(公告)日：2018-12-04

申请号：US14998085

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: G06F12/00 ,  G06F12/02

Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.

公开(公告)号：US20180234486A1

公开(公告)日：2018-08-16

申请号：US15434726

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Nicolas A. Salhuana ,  Daniel Rivas Barragan

IPC: H04L29/08 ,  H04L29/06

Abstract: A computing device, method and system to implement an adaptive compression scheme in a network fabric. The computing device may include a memory device and a fabric controller coupled to the memory device. The fabric controller may include processing circuitry having logic to communicate with a plurality of peer computing devices in the network fabric. The logic may be configured to implement the adaptive compression scheme to select, based on static information and on dynamic information relating to a peer computing device of the plurality of peer computing devices, a compression algorithm to compress a data payload destined for the peer computing device, and to compress the data payload based on the compression algorithm. The static information may include information on data payload decompression supported methods of the peer computing device, and the dynamic information may include information on link load at the peer computing device. The compression may further take into consideration QoS requirements of the data payload. The computing device may send the data payload to the peer computing device after compressing.

公开(公告)号：US10031699B1

公开(公告)日：2018-07-24

申请号：US15787626

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Benjamin A. Graniello ,  Karthik Kumar

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/22 ,  G11C7/10

Abstract: Technology for a system operable to write and read data from memory is described. The system can include memory and a memory controller. The memory controller can send an instruction to write data to a NVM address in the memory at a time of last write (TOLW). The memory controller can determine to read the data from the NVM address in the memory at read time. The memory controller can determine a read voltage to read the data from the NVM address in the memory at the read time. The read voltage can be determined based on a difference between the TOLW and the read time, and a modeled voltage drift for the NVM address over a period of time.

公开(公告)号：US20170353576A1

公开(公告)日：2017-12-07

申请号：US15170094

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: H04L29/08 ,  G06F12/0862

CPC classification number: H04L67/2847 ,  G06F12/0862 ,  G06F2212/154 ,  G06F2212/602 ,  G06F2212/6022

Abstract: In one embodiment, an apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.

公开(公告)号：US20170168942A1

公开(公告)日：2017-06-15

申请号：US14965487

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Brian Slechta

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/12 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/2542 ,  G06F2212/314 ,  G06F2212/621

Abstract: Technologies for managing cache memory of a processor in a distributed shared memory system includes managing a distance value and an age value associated with each cache line of the cache memory. The distance value is indicative of a distance of a memory resource, relative to the processor, from which data stored in the corresponding chance line originates. The age value is based on the distance value and the number of times for which the corresponding cache line has been considered for eviction since a previous eviction of the corresponding cache line. Initially, the age value is set to the distance value. Additionally, every time a cache line is accessed, the age value associated with the accessed cache line is reset to the corresponding distance value. During a cache eviction operation, the cache line for eviction is selected based on the age value associated with each cache line. The age values of cache lines not selected for eviction are subsequently decremented such that even cache lines associated with remote memory resources will eventually be considered for eviction if not recently accessed.