公开(公告)号：US10483963B2

公开(公告)日：2019-11-19

申请号：US15878363

申请日：2018-01-23

Applicant: RichWave Technology Corp.

Inventor： Juang-Shiung Wu

IPC: H03K17/22 ,  H03L7/08 ,  H03L7/18

Abstract: A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

公开(公告)号：US20190229532A1

公开(公告)日：2019-07-25

申请号：US16168845

申请日：2018-10-24

Applicant: RichWave Technology Corp.

Inventor： Chuan-Chen Chao

IPC: H02H9/04 ,  H03K17/693 ,  G05F3/18 ,  H02H9/02

Abstract: A switch apparatus is provided. The switch apparatus includes a signal control switch, a switch circuit, a blocking capacitor and a surge current dissipation circuit. The signal control switch and the switch circuit are respectively controlled by a first control signal and a second control signal to be turned on or off. The blocking capacitor is serially coupled between the switch circuit and a reference voltage end. The surge current dissipation circuit includes a Zener diode circuit or at least one diode circuit, and the at least one diode circuit has one or more diodes coupled in series. The one or more diodes coupled in series are coupled between two ends of the surge current dissipation circuit according to a first polarity direction.

公开(公告)号：US10340878B2

公开(公告)日：2019-07-02

申请号：US15949024

申请日：2018-04-09

Applicant: RichWave Technology Corp.

Inventor： Wei-Kung Deng ,  Chih-Min Chiang

IPC: H03H7/38 ,  H03F3/19 ,  H01P5/12

Abstract: A carrier aggregation circuit includes a signal input terminal, a signal output terminal, a first filter, a first output transform circuit, a second filter, and a second output transform circuit. The signal input terminal receives a radio frequency signal with carrier waves with first and second carrier wave frequencies. The first filter and the second filter are coupled between the signal input terminal and the signal output terminal respectively, and can respectively filter out signals with frequencies other than the first and the second carrier wave frequencies. The first output transform circuit is coupled between the first filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the second carrier frequency. The second output transform circuit is coupled between the second filter and the signal output terminal, and has an output impedance equivalent to an open circuit at the first carrier frequency.

公开(公告)号：US10326406B2

公开(公告)日：2019-06-18

申请号：US15718079

申请日：2017-09-28

Applicant: RICHWAVE TECHNOLOGY CORP.

Inventor： Chih-Sheng Chen ,  Hong-Jia Lo

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/21 ,  H03F3/19

Abstract: An amplifier device includes an amplifying unit, a bias module and an impedance unit. A first end of the amplifying unit electronically connects to a voltage source. A second end of the amplifying unit receives an input signal. The first end of the amplifying unit outputs an output signal amplified by the amplifying unit. A third end of the amplifying unit connects to a first reference potential. The bias module electrically connects to the second end of the amplifying unit for providing a bias voltage to the amplifying unit. An impedance unit is electrically connects to the bias module. An impedance value of the impedance unit is variable. The bias module adjusts the amplifier's linearity according to a frequency value of the input signal, a voltage value of the voltage source or a temperature value of the amplifier device. The impedance is adjusted according to the above-mentioned values.

公开(公告)号：US10270349B2

公开(公告)日：2019-04-23

申请号：US15398726

申请日：2017-01-05

Applicant: RichWave Technology Corp.

Inventor： Chih-Sheng Chen ,  Tien-Yun Peng

IPC: H02M3/24 ,  H02M3/07 ,  H02M1/36 ,  H02M7/10

Abstract: A voltage generator including an oscillator having an output, a charge pump having an input and an output, the input of the charge pump being coupled to the output of the oscillator, a smoothing capacitor, a resistor having an input end and an output end, wherein the input end is coupled to the charge pump and the output end is coupled to the smoothing capacitor, and a shorting element connected in parallel with the resistor and which, when turned on, causes the resistor to be at least partially bypassed, wherein the voltage generator is configured to supply voltage to a radio frequency (RF) switch via the smoothing capacitor, and a frequency of the oscillator is controlled to be faster during a switching period of the RF switch.

公开(公告)号：US20180275709A1

公开(公告)日：2018-09-27

申请号：US15839189

申请日：2017-12-12

Applicant: RICHWAVE TECHNOLOGY CORP.

Inventor： Chih-Sheng Chen ,  Tien-Yun Peng ,  Jhao-Yi Lin

IPC: G05F3/16 ,  H03F5/00 ,  H01L27/06 ,  H03F1/30

CPC classification number: G05F3/16 ,  H01L27/0629 ,  H03F1/223 ,  H03F1/301 ,  H03F1/302 ,  H03F5/00 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/294 ,  H03F2200/451

Abstract: A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor.

公开(公告)号：US20180234057A1

公开(公告)日：2018-08-16

申请号：US15805125

申请日：2017-11-06

Applicant: RichWave Technology Corp.

Inventor： Chih-Sheng Chen ,  Pei-Chuan Hsieh

IPC: H03F1/32 ,  H03F3/21 ,  H03F3/19 ,  H03F1/02

CPC classification number: H03F1/3241 ,  H03F1/0205 ,  H03F1/0261 ,  H03F1/3276 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/18 ,  H03F2200/451

Abstract: A predistorter has a first capacitor and an impedance conversion circuit. A first end of the first capacitor is coupled to a first node of the amplifier. The impedance conversion circuit is used to perform an impedance conversion to provide a variable capacitance. The impedance conversion circuit has a first bias input circuit and a bipolar junction transistor (BJT). The first bias input circuit is used to receive a first input bias. A base of the BJT is coupled to an output end of the first bias input circuit and a second end of the first capacitor, a collector of the BJT is floating, and an emitter of the BJT is coupled to a second node of the amplifier.

公开(公告)号：US10027289B2

公开(公告)日：2018-07-17

申请号：US15469566

申请日：2017-03-26

Applicant: RichWave Technology Corp.

Inventor： Chih-Sheng Chen ,  Chang-Yi Chen

IPC: H03F3/04 ,  H03F1/56 ,  H03F3/16

CPC classification number: H03F1/56 ,  H03F1/0277 ,  H03F1/223 ,  H03F3/16 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/555 ,  H03F2203/7239

Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.

公开(公告)号：US20180191305A1

公开(公告)日：2018-07-05

申请号：US15658409

申请日：2017-07-25

Applicant: RichWave Technology Corp.

Inventor： Hwey-Ching Chien

IPC: H03F1/02 ,  H03F3/04

CPC classification number: H03F1/02 ,  G01R19/00 ,  G01R19/0092 ,  H03F3/04

Abstract: A signal detector includes a signal input terminal, N first resistors, (N−1) second resistors, a third resistor, M voltage-to-current units and a collection unit. A first terminal of a 1st first resistor is coupled to the signal input terminal. A first terminal of an ith first resistor is coupled to a second terminal of an (i−1)th first resistor. A first terminal of a kth second resistor is coupled to a second terminal of a kth first resistor. A second terminal of each second resistor is coupled to a reference voltage terminal. The third resistor is coupled between the reference voltage terminal and a second terminal of an Nth first resistor. Each voltage-to-current unit is coupled to a first terminal of a corresponding first resistor for converting a corresponding detection voltage to a detection current. The collection unit is coupled to the M voltage-to-current units for generating a detection signal according to at least the M detection currents.

公开(公告)号：US09813268B2

公开(公告)日：2017-11-07

申请号：US15222937

申请日：2016-07-28

Applicant: RichWave Technology Corp.

Inventor： Zhuo Fu

IPC: H04L27/00 ,  H04L27/12 ,  H04L27/227 ,  H04L27/148

CPC classification number: H04L27/122 ,  H04L27/0014 ,  H04L27/148 ,  H04L27/2275 ,  H04L2027/0026

Abstract: A digital frequency modulation receiver includes a phase capturer, an adder, a digital filter and a phase estimator. The phase estimator is used to generate a first phase value according to an input signal. The adder is coupled to the phase estimator for subtracting a second phase value from the first phase value to generate a phase difference. The digital filter is coupled to the adder for performing a filtering calculation with the phase difference so as to generate a frequency variation signal. The phase estimator is coupled to the digital filter and the adder so as to update the second phase value according to the frequency variation signal.