公开(公告)号：US20020167356A1

公开(公告)日：2002-11-14

申请号：US10144623

申请日：2002-05-13

Applicant: STMicroelectronics S.A.

Inventor： Claude Renous ,  Francois Van-Zanten

IPC: H03F003/45

CPC classification number: H03F3/3023 ,  H03F3/45188 ,  H03F3/45659 ,  H03F2203/45711

Abstract: A wideband differential amplifier includes a first differential stage connected to a Miller stage allowing an open-loop gain increase. The Miller stage includes a current source and a resistive-capacitive network causing a feedback into the current source. The feedback includes a portion of a Miller stage output signal having a high frequency range to move a bias point of the current source within the high frequency range. Thus, a gain of the Miller stage significantly increases towards the bias point.

Abstract translation: 宽带差分放大器包括连接到Miller级的第一差分级，允许开环增益增加。 米勒级包括电流源和电阻电容网络，导致反馈到电流源。 反馈包括具有高频范围的米勒级输出信号的一部分，以将电流源的偏置点移动到高频范围内。 因此，米勒阶段的增益显着地朝向偏向点增加。

公开(公告)号：US20020162677A1

公开(公告)日：2002-11-07

申请号：US10136682

申请日：2002-05-01

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Christian Caillat

IPC: H02G003/08

CPC classification number: H01L28/40 ,  H01L21/3144 ,  H01L23/5223 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated component, in which process and component a first electrode is in the form of a cup; a layer made of a dielectric covers at least the wall of the first electrode; a second electrode fills the cup; a first electrical connection via lies above the second electrode; and a second electrical connection via lies laterally with respect to and at a predetermined distance from the first electrode and is connected to the first electrode.

Abstract translation: 用于制造组件的方法，例如集成电路中的电容器和集成部件，其中第一电极是杯形式的工艺和部件; 由电介质覆盖的层至少覆盖第一电极的壁; 第二电极填充杯子; 第一电连接通孔位于第二电极上方; 并且第二电连接通孔相对于第一电极相对于并且距离第一电极具有预定距离横向延伸并且连接到第一电极。

公开(公告)号：US20020147901A1

公开(公告)日：2002-10-10

申请号：US10083629

申请日：2002-02-26

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler

IPC: G06F009/00

CPC classification number: G06F9/3814 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3889

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

Abstract translation: 处理单元与第一FIFO型存储器和第二FIFO型存储器相关联。 用于将存储器存储的数据加载到处理单元内的寄存器的每个指令被存储在第一FIFO型存储器中，并且其它操作指令被存储在第二FIFO型存储器中。 如果在第一FIFO型存储器中不存在用于修改与该操作指令相关联的寄存器的值的时间上的加载指令，则从第二FIFO型存储器移除涉及寄存器的操作指令。 在存在这种较早的加载指令的情况下，仅在从第一FIFO型存储器移除了加载指令之后，将操作指令从第二FIFO型存储器中移除。

公开(公告)号：US20020145446A1

公开(公告)日：2002-10-10

申请号：US10073680

申请日：2002-02-11

Applicant: STMicroelectronics S.A.

Inventor： Leila Aitouarab

IPC: H03K019/094

CPC classification number: H03K17/693 ,  H03K3/356147 ,  H03K17/102

Abstract: A voltage-switching device includes a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low-voltage/high-voltage mode control signal to provide at least one output signal as a function of this mode control signal and of a switching control signal. A voltage-level switching circuit is controlled by output signals from the high-voltage translator and by the mode control signal and the switching control signal for application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the high-voltage level in high-voltage mode.

Abstract translation: 电压切换装置包括连接到接收低电压逻辑电平或高电压电平的高压节点的高压转换器，作为低电压/高电压模式控制信号的函数，以提供 作为该模式控制信号和切换控制信号的函数的至少一个输出信号。 电压电平开关电路由来自高电压转换器的输出信号和模拟控制信号和用于施加的开关控制信号控制，作为低电压的接地或低电压逻辑电平的输出电压电平 模式或高电压电平。

公开(公告)号：US20020135379A1

公开(公告)日：2002-09-26

申请号：US10060105

申请日：2002-01-29

Applicant: STMicroelectronics S.A.

Inventor： Christophe Moreaux ,  Ahmed Kari

IPC: G01R031/00

CPC classification number: G01R31/043

Abstract: A device for detecting a defective power supply connection in an integrated circuit includes a comparison circuit for comparing voltage levels of an input/output pad of the integrated circuit and an internal power supply line connected to a power supply pad of the integrated circuit. A pull-down or pull-up device is connected between the input/output pad and the internal power supply line.

Abstract translation: 用于检测集成电路中的有缺陷的电源连接的装置包括比较电路，用于比较集成电路的输入/输出焊盘的电压电平和连接到集成电路的电源焊盘的内部电源线。 在输入/输出板和内部电源线之间连接一个下拉或上拉设备。

公开(公告)号：US20020135020A1

公开(公告)日：2002-09-26

申请号：US10084255

申请日：2002-02-27

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Alexandre Villaret

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76289 ,  H01L29/66772

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract translation: 源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。

公开(公告)号：US20020129219A1

公开(公告)日：2002-09-12

申请号：US10081740

申请日：2002-02-22

Applicant: STMicroelectronics S.A.

Inventor： Yvon Bahout

IPC: G06F012/02

CPC classification number: G11C8/04

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract translation: 依次读取实现增量地址计数器的存储器。 地址跳转包括检测地址跳转信号，递增增量地址计数器以及以递增的地址读取存储器的内容。 在增量地址读取的内容被传送到增量地址计数器，并且在包含在增量地址计数器中的地址读取存储器的内容。

公开(公告)号：US20020126548A1

公开(公告)日：2002-09-12

申请号：US10044307

申请日：2001-10-26

Applicant: STMicroelectronics S.A.

Inventor： Jerome Ciavatti

IPC: H01L021/8242

CPC classification number: H01L21/76897 ,  H01L27/10888 ,  Y10S438/954

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract translation: 一种用于制造DRAM单元的方法，所述DRAM单元包括具有漏极区和不同源极区的两个有源字线，包括在形成绝缘导线之后的步骤：沉积第一，然后第二可选择蚀刻的绝缘层; 蚀刻第二绝缘层以仅将其保持在导电线之上; 沉积和调平相对于至少第二绝缘层可选择性蚀刻的第三绝缘层; 打开第一和第三绝缘层以暴露漏极区域和绝缘沟槽; 用导电材料填充先前形成的开口; 抛光整个结构; 以及沉积相对于所述第三绝缘层可选择性蚀刻的第四绝缘层。

公开(公告)号：US20020125866A1

公开(公告)日：2002-09-12

申请号：US10052209

申请日：2002-01-16

Applicant: STMicroelectronics, S.A.

Inventor： Cecile Hamon ,  Christophe Bernard ,  Alexandre Pons

IPC: G05F001/40

CPC classification number: G05F1/46 ,  H03K17/122

Abstract: A voltage regulator having an output terminal provided for being connected to a load, including an amplifier having its inverting input connected to a reference voltage, and its non-inverting input connected to the output terminal, a charge capacitor arranged between the output terminal and a first supply voltage, first and second voltage-controlled switches each arranged to connect a second supply voltage and the output terminal, and a control means adapted to providing a voltage depending on the output voltage of the amplifier, on the one hand, to the gate of the first switch and, on the other hand, when the current flowing through the first switch reaches a predetermined threshold, to the gate of the second switch.

Abstract translation: 一种电压调节器，其具有设置用于连接到负载的输出端子，包括具有连接到参考电压的反相输入的放大器，以及连接到输出端子的其非反相输入端，布置在输出端子和 第一电源电压，第一和第二电压控制开关，每个被布置成连接第二电源电压和输出端子;以及控制装置，一方面提供取决于放大器的输出电压的电压， 并且另一方面，当流过第一开关的电流达到预定阈值时，到达第二开关的栅极。

公开(公告)号：US20020109491A1

公开(公告)日：2002-08-15

申请号：US09953071

申请日：2001-09-14

Applicant: STMicroelectronics S.A.

Inventor： Edith Kussener

IPC: G05F003/16

CPC classification number: G05F3/30 ,  Y10S323/907

Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.

Abstract translation: 调节电压发生器为集成电路提供不同的调节电压。 调节电压发生器包括带隙参考电路和连接到其输出的至少一个增益级。 带隙参考电路的输出电压作为温度的函数而变化，以补偿由第​​一和第二晶体管构成的增益级的变化。 调节电压发生器的稳压输出与温度和电源电压无关。 调节电压的值通过负载电阻器和第一和第二晶体管以及带隙基准电路的输出晶体管进行调整。