公开(公告)号：WO2006090417A1

公开(公告)日：2006-08-31

申请号：PCT/IT2005/000110

申请日：2005-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

Inventor： MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

IPC: H01L21/768 ,  B82B1/00

CPC classification number: B82Y10/00 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for realising a nanometric circuit architecture (2) in a semiconductor device comprising the steps of: a) realising a plurality of active areas (1) on a substrate (A) of the semiconductor device; b) realising on the substrate (A) a seed layer (4) of a first material; c) realising a mask-spacer (5) of a second material on the seed layer (4) in a region (A’) of the substrate (A) comprised between said active areas (1), said mask-spacer (5) being realised by MSPT and having at least one end portion (5) extending over the region (A’); d) realising at least one mask (6) overlapping the mask-spacer (5) and extending in a substantially perpendicular direction thereto (5); e) selectively removing the seed layer (4) being exposed on the substrate (A); f) selectively removing the mask (6) and the mask-spacer (5) obtaining a seed-spacer (7; 70) comprising a linear portion (7a) extending in that region (A’) and connected to at least one portion (7b) being substantially orthogonal thereto; g) eventually realising at least one insulating spacer (8) from said seed-spacer (7; 70) through the MSPT, that at least one insulating spacer (8) reproducing at least part of the profile of said seed-spacer (7; 70); h) realising at least one nano-wire (3; 13; 23) of conductive material from the seed-spacer (7, 70) or from the at least one insulating spacer (8) through the MSPT, the at least one nano-wire (3; 13; 23; 33) comprising a first portion (3a; 13a) at least partially extending in said region (A’) and at least one second portion (3b; 13b) in contact with a respective active area (1), the second portion (3b; 13b) being substantially orthogonal to the first portion (3a; 13a).

Abstract translation: 本发明涉及一种在半导体器件中实现纳米电路结构（2）的方法，包括以下步骤：a）在半导体器件的衬底（A）上实现多个有源区（1）; b）在基板（A）上实现第一材料的种子层（4）; c）在所述有源区（1），所述掩模间隔物（5）之间的衬底（A）的区域（A'）中实现种子层（4）上的第二材料的掩模间隔物（5） 通过MSPT实现并且具有在区域（A'）上延伸的至少一个端部（5）; d）实现与所述掩模间隔件（5）重叠并沿基本垂直的方向（5）延伸的至少一个掩模（6）; e）选择性地去除暴露在基底（A）上的种子层（4）; f）选择性地去除掩模（6）和掩模间隔物（5），获得包括在该区域（A'）中延伸并连接到至少一个部分（A'）的直线部分（7a）的种子间隔物（7; 70） 7b）基本上与其正交; g）最终通过MSPT从所述种子间隔物（7; 70）中实现至少一个绝缘间隔物（8），至少一个绝缘间隔物（8）再现至少部分所述种子间隔物（7; 70）; h）从所述种子间隔物（7,70）或通过所述MSPT从所述至少一个绝缘间隔物（8）实现至少一个导电材料的纳米线（3; 13; 23），所述至少一个纳米线 包括在所述区域（A'）中至少部分地延伸的第一部分（3a; 13a）和与相应的有效区域（1）接触的至少一个第二部分（3b; 13b）的导线（3; 13; 23; 33） ），所述第二部分（3b; 13b）基本上与所述第一部分（3a; 13a）正交。

公开(公告)号：WO2006032622A1

公开(公告)日：2006-03-30

申请号：PCT/EP2005/054568

申请日：2005-09-14

Applicant: STMICROELECTRONICS S.R.L. ,  POZZI, Massimiliano ,  D'ANGELO, Gianfranco

Inventor： POZZI, Massimiliano ,  D'ANGELO, Gianfranco

IPC: B24B53/007 ,  B24B37/04

CPC classification number: B24B53/017

Abstract: The present invention refers to a multi-station rotary machine for polishing wafers, comprising a machine body (1) and a rotating tower (2) consisting of a plurality of heads (3) each of which supports a wafer (4). Said tower (2) made to rotate with predefined pitch between a first station (25) for loading/unloading the wafers (4) and subsequent work stations all the same in which said heads (3) position themselves on rotatable polishing plates (5) on which rotating cleaning arms (6) act in the work phase with rotation pin and rotating end (7) in contact with the above mentioned plates (5). Between said work stations intermediate washing zones of the heads (3) and the wafers (4) are provided for by means of cleaning means (8, 17) that comprise delivery blocks (8) of washing liquid positioned between said plates (5) and each one having an upper hole (9) for the delivery of a nozzle (11) spraying liquid under pressure for cleaning one of said heads (3) and the lower part of the tower (2), and a supplementary hole connected to a further nozzle (13) for cleaning the machine body (1) and the rotation pin of one of said cleaning arms (6). Said cleaning means also comprise arms (17) for delivering the washing liquid positioned above said plates (5) with external support and each one having a supplementary lower hole (20) connected to a tube (21) that carries the liquid towards a further nozzle (22) for cleaning the lower part of said rotating arms (6) when they are in the rest position.

Abstract translation: 本发明涉及一种用于抛光晶片的多工位旋转机，包括机体（1）和由多个头（3）组成的旋转塔（2），每个头（3）支撑晶片（4）。 所述塔架（2）在用于装载/卸载晶片（4）的第一工位（25）和所有头部（3）自身位于可旋转的抛光板（5）上的所有相同的工作站之间以预定的间距旋转， 在旋转销和与上述板（5）接触的旋转端（7）上，旋转清洁臂（6）在工作相中作用。 在所述工作站之间，通过清洁装置（8,17）提供头部（3）和晶片（4）的中间洗涤区域，所述清洁装置包括位于所述板（5）和 每个具有用于输送喷嘴（11）的喷嘴（11）的上孔（9），用于在压力下喷射液体以清洁所述头部（3）和塔架（2）的下部之一;以及辅助孔，其连接到另一个 用于清洁机体（1）的喷嘴（13）和所述清洁臂（6）之一的旋转销。 所述清洁装置还包括用于通过外部支撑件输送位于所述板（5）上方的洗涤液的臂（17），并且每个具有连接到管（21）的辅助下孔（20），所述管（21）将液体朝向另一个喷嘴 （22），用于当它们处于静止位置时清洁所述旋转臂（6）的下部。

公开(公告)号：WO2005093664A1

公开(公告)日：2005-10-06

申请号：PCT/IB2005/000117

申请日：2005-01-14

Applicant: STMICROELECTRONICS S.R.L. ,  GARDELLA, Pierluigi ,  BARONE, Massimiliano ,  GALLIZIO, Edoardo ,  PAU, Danilo

Inventor： GARDELLA, Pierluigi ,  BARONE, Massimiliano ,  GALLIZIO, Edoardo ,  PAU, Danilo

IPC: G06T11/40

CPC classification number: G06T11/40

Abstract: A system for rendering a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system is configured for: - locating the pixels that fall within the area of the primitive, - generating, for each pixel located in the area, a set of associated sub-pixels, - borrowing a borrowed set of sub-pixels from neighboring pixels, - subjecting the set of associated sub-pixels and the borrowed set of pixels (A, B, C, D) to adaptive filtering to create an' adaptively filtered set of sub­pixels (AA, BB, CC, DD), and - subjecting at least the adaptively filtered set of sub-pixels (AA, BB, CC, DD) to further filtering to compute a final pixel adapted for display. Preferably, the set of associated sub-pixels fulfils at least one of the following requirements: the set includes two associated sub-pixels and - the set includes associated sub-pixels placed on triangle edges.

Abstract translation: 用于渲染要显示的图像的原语的系统，例如在移动3D图形流水线中，所述图元包括一组像素。 该系统被配置为： - 定位落在基元区域内的像素， - 为位于该区域中的每个像素产生一组相关联的子像素， - 从相邻像素借用借用的子像素组 - 对所述一组相关联的子像素和所借用的像素组（A，B，C，D）进行自适应滤波以创建“自适应滤波的子像素组（AA，BB，CC，DD）”，以及 - 至少自适应滤波的子像素组（AA，BB，CC，DD）进一步滤波以计算适于显示的最终像素。 优选地，该组相关联的子像素满足以下要求中的至少一个：该集合包括两个相关联的子像素，并且 - 该集合包括放置在三角形边缘上的相关联的子像素。

公开(公告)号：WO2005091481A1

公开(公告)日：2005-09-29

申请号：PCT/EP2005/050880

申请日：2005-03-01

Applicant: STMICROELECTRONICS S.R.L. ,  ADRAGNA, Claudio

Inventor： ADRAGNA, Claudio

IPC: H02M1/00

CPC classification number: H02M1/32

Abstract: The present invention relates to switching. power supplies, and especially to a method and the related circuit for protection against malfunctioning of the feedback loop in switching power supplies. More particularly it relates to a circuit for the identification of a condition of excessively high voltage at the output. In one embodiment the circuit for the protection against malfunctioning of the feedback loop of a switching power supply comprises: means for generating (vaux R1, R2) a voltage proportional to the output voltage of said switching power supply; a comparator (15) for comparing said voltage proportional to the output voltage with a reference voltage (vth); a counter (17) coupled to said comparator capable of supplying an output signal when said voltage proportional to the output voltage exceeds said reference voltage a preset number of times; said output signal is indicative of a malfunctioning of the feedback loop.

Abstract translation: 本发明涉及切换。 电源，特别是用于防止开关电源中的反馈回路故障的方法和相关电路。 更具体地说，涉及用于识别输出端的过高电压条件的电路。 在一个实施例中，用于防止开关电源的反馈回路故障保护的电路包括：用于产生与所述开关电源的输出电压成比例的电压的装置（vaux R1，R2） 比较器（15），用于将与输出电压成比例的所述电压与参考电压（vth）进行比较; 当与所述输出电压成比例的所述电压超过所述参考电压预定次数时，耦合到所述比较器的计数器（17）能够提供输出信号; 所述输出信号表示反馈回路的故障。

公开(公告)号：WO2005079053A1

公开(公告)日：2005-08-25

申请号：PCT/IT2005/000080

申请日：2005-02-16

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS LTD. ,  GARDELLA, Pier Luigi ,  BARONE, Massimiliano ,  SWEET, Gary ,  PAU, Danilo ,  HILL, Stephen? ,  GODA, Simon

Inventor： GARDELLA, Pier Luigi ,  BARONE, Massimiliano ,  SWEET, Gary ,  PAU, Danilo ,  HILL, Stephen? ,  GODA, Simon

IPC: H04N1/41

CPC classification number: H04N19/00 ,  G09G3/2051 ,  G09G5/02 ,  H04N1/40087 ,  H04N19/42 ,  H04N19/90

Abstract: An ordered dither method is applied to reduce the chromatic resolution of an image represented by channels R (red), G (green), B (blue) and A (brightness), whereby a first and a second dither matrix is provided, both comprising the same threshold values but arranged in a different spatial distribution. The first dither matrix is applied to the R, B, and A channels, and the second dither matrix is applied to the G channel.

Abstract translation: 应用有序抖动方法来降低由通道R（红色），G（绿色），B（蓝色）和A（亮度）表示的图像的色度分辨率，由此提供第一和第二抖动矩阵， 相同的阈值但排列在不同的空间分布。 第一个抖动矩阵被施加到R，B和A信道，第二个抖动矩阵被施加到G信道。

公开(公告)号：WO2004047328A1

公开(公告)日：2004-06-03

申请号：PCT/EP2002/012815

申请日：2002-11-15

Applicant: TELECOM ITALIA S.P.A. ,  STMICROELECTRONICS S.R.L. ,  ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  OSSOLI, Alessandro ,  RUSCITTO, Alfredo

Inventor： ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  OSSOLI, Alessandro ,  RUSCITTO, Alfredo

IPC: H04B1/707

CPC classification number: H04B1/7093 ,  H04B1/7113 ,  H04B1/7117 ,  H04B2201/70707

Abstract: A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffer (16), each addressing operation corresponding to a new correlation operation of the basic correlator (32) for the computation of a new value of the channel delay profile energy (DP(l)).

Abstract translation: 包括用于存储输入信号（y（k））的采样的输入存储器缓冲器（16）和用于生成重新生成的用户代码的代码生成器电路（30）的类型的扩展频谱数字通信接收机包括一个 用于估计信道延迟分布的装置（24）包括：基本相关器（32），具有用于从输入存储器缓冲器（16）的存储器位置顺序读取输入信号的多个样本的第一输入端（41） （y（k）），用于从码发生器电路（30）接收重新生成的用户码的第二输入端（43），以及输出端子，用于通过所述多个采样 输入信号和再生用户代码，信道延迟分布能量（DP（1））的第一值; 以及存储器控制器电路（36），用于寻址所述存储器缓冲器（16），使得所述基本相关器（32）的第一输入端（41）被连续地馈送到所述存储器缓冲器（16）的若干存储器位置的内容， 每个寻址操作对应于用于计算信道延迟分布能量（DP（1））的新值的基本相关器（32）的新的相关操作。

公开(公告)号：WO2004047326A1

公开(公告)日：2004-06-03

申请号：PCT/EP2002/012813

申请日：2002-11-15

Applicant: TELECOM ITALIA S.P.A. ,  STMICROELECTRONICS S.R.L. ,  ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  RUSCITTO, Alfredo

Inventor： ETTORRE, Donato ,  GRAZIANO, Maurizio ,  MELIS, Bruno ,  FINOTELLO, Andrea ,  RUSCITTO, Alfredo

IPC: H04B1/707

CPC classification number: H04B1/7085 ,  H04B1/70757

Abstract: A method for the synchronization of a digital telecommunication receiver comprises the steps of: - storing a plurality of consecutive samples E-l, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant; - calculating an error signal ξ as the difference between the energy of the symbols computed from the interpolated early sample (e) and the interpolated late (1) sample; - extracting the sign of the error signal ξ - accumulating the sign of the error signal ξ for the generation of control signals S E , S M , S L for controlling the interpolation phases of the digitally controlled interpolators used for determining the interpolated early (e), middle (m) and late (l) samples. The accumulated value has a positive saturation value of +4 and a negative saturation value of 4.

Abstract translation: 一种用于数字电信接收机同步的方法包括以下步骤： - 在延迟线56中存储输入扩频信号的多个连续样本E-1，E，M，L，L + 1; - 通过第一数字控制内插器26来确定进入的扩频信号的连续采样之间的插值，预测最佳采样时刻的内插早期采样（e）; - 通过第二数字控制内插器24确定进入的扩频信号的连续采样之间的插值，对应于最佳采样时刻的内插中间采样（m）; - 通过第三数字控制内插器28确定进入的扩展频谱信号的连续样本之间的内插，相对于最佳采样时刻延迟的内插后采样（1）; 将误差信号xi计算为从插值的早期样本（e）和插值的深（1）样本计算的符号的能量之间的差; - 提取误差信号xi的符号 - 累积误差信号xi的符号以产生控制信号S> E <，S> M <，S> L <用于控制用于数字控制内插器的内插相位 确定内插的早期（e），中（m）和晚（l）样本。 累积值的正饱和值为+4，负饱和值为4。

公开(公告)号：WO2004027965A1

公开(公告)日：2004-04-01

申请号：PCT/IT2002/000602

申请日：2002-09-20

Applicant: STMICROELECTRONICS S.R.L. ,  PIDUTTI, Albino ,  ADRAGNA, Claudio ,  FAGNANI, Mauro

Inventor： PIDUTTI, Albino ,  ADRAGNA, Claudio ,  FAGNANI, Mauro

IPC: H02M1/00

CPC classification number: H02M1/4225 ,  Y02B70/126

Abstract: A power factor correction device for switching power supplies is described, which comprises a converter (20) and a control device (100;200;300) coupled with said converter (20) in such a way as to obtain from a input network alternated voltage (Vin) a direct regulated voltage (Vout) at the output terminal. The converter (20) comprises a power transistor (M) and the control device (100;200;300) comprises an error amplifier (3) having in input at the inverting terminal a first signal (Vr) proportional to said regulated voltage (Vout) at at the non-inverting terminal a voltage reference (Vref), at least one capacitor (C) having a first terminal and a second terminal which are coupled respectively with the inverting terminal and the output terminal (31) of the error amplifier (3) and a driving circuit (4-6) of said power transistor (M) which is coupled with the second terminal of said capacitor (C). The control device (100;200;300) comprises interruption means (SW)placed between the output terminal (31) of said error amplifier (3) and said driving circuit (4-6) for at least one time period (T) lower than the time period (Tciclo) in which said control device (100; 200; 300) is operative.

Abstract translation: 描述了用于开关电源的功率因数校正装置，其包括与所述转换器（20）耦合的转换器（20）和控制装置（100; 200; 300），以便从输入网络获得交替电压 （Vin）在输出端子处的直接调节电压（Vout）。 所述转换器（20）包括功率晶体管（M），所述控制装置（100; 200; 300）包括误差放大器（3），所述误差放大器（3）在所述反相端子处具有与所述调节电压（Vout ）在非反相端子处具有电压基准（Vref），至少一个具有第一端子和第二端子的电容器（C），其分别与误差放大器的反相端子和输出端子（31）耦合 3）和与所述电容器（C）的第二端子耦合的所述功率晶体管（M）的驱动电路（4-6）。 控制装置（100; 200; 300）包括放置在所述误差放大器（3）的输出端（31）和所述驱动电路（4-6）之间的至少一个时间段（T）较低的中断装置（SW） 比所述控制装置（100; 200; 300）可操作的时间段（Tciclo）高。

公开(公告)号：WO2004010569A1

公开(公告)日：2004-01-29

申请号：PCT/IT2002/000478

申请日：2002-07-19

Applicant: STMICROELECTRONICS S.R.L. ,  FAGNANI, Mauro ,  PIDUTTI, Albino ,  ADRAGNA, Claudio

Inventor： FAGNANI, Mauro ,  PIDUTTI, Albino ,  ADRAGNA, Claudio

IPC: H02M1/00

CPC classification number: H02M1/36 ,  H02M3/335 ,  H02M2001/0006

Abstract: The present invention refers to a starting circuit for switching power supplies (SMPS), to a switching power supply comprising a starting circuit )and an integrated circuit of a switching power supply. In an embodiment thereof the starting circuit (13) for switching power supplies having a first supply voltage (Vin) coming from a first terminal and a second supply voltage (Vcc) coming from a second terminal and a third tenninal (30); said starting circuit comprises: a first current path between said first terminal and said third terminal (30); a second current path between said first tenninal and said second terminal; a third current path between said second terminal and said third terminal (30); a two-way voltage regulator (M3, Dz2, R5, R6) placed along said second current path.

Abstract translation: 本发明涉及用于切换电源（SMPS）的起动电路，包括起动电路的开关电源）和开关电源的集成电路。 在其实施例中，用于切换来自第一端子的第一电源电压（Vin）和来自第二端子和第三端子（30）的第二电源电压（Vcc）的电源的启动电路（13）。 所述启动电路包括：在所述第一端子和所述第三端子之间的第一电流路径; 所述第一终端和所述第二终端之间的第二电流路径; 所述第二端子和所述第三端子之间的第三电流通路; 沿着所述第二电流路径放置的双向电压调节器（M3，Dz2，R5，R6）。

公开(公告)号：WO2003007479A1

公开(公告)日：2003-01-23

申请号：PCT/EP2002/006487

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23"). A logic unit (17") controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23"). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

Abstract translation: 以二进制码加权的采样电容器的第一阵列（10A'）的电容器连接在第一公共电路节点（NB +）和要被充电到相对于地的电压（Vin）的输入端子（Gnd）之间 然后根据BAR技术选择性地连接两个差分参考端（Vrefp，Vrefm），同时将第一阵列（10B'）的电容等于第一阵列（10B'），并将其全部连接到 第二节点（NB-）选择性地连接到地（Gnd）和下差分电压端（Vrefm）。 两个节点连接到比较器（23“）的相应输入端，逻辑单元（17”）根据预定的定时程序控制两个阵列的电容器的连接，并根据 比较器（23“）虽然转换器具有单端输入，但它的作用就像具有差分输入的转换器20，因此在噪声方面具有优异的抗扰度，而且不需要额外的电容器或特别敏感的 比较器，其特征在于低功耗和高速度，占据其形成部分的集成电路的非常小的面积。