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    소프트웨어 성능 프로파일링 데이터 포획용 캐시가 합체된 마이크로프로세서 기반 장치
    263.
    发明公开
    소프트웨어 성능 프로파일링 데이터 포획용 캐시가 합체된 마이크로프로세서 기반 장치 有权
    软件性能分析基于微处理器的设备整合了数据捕获缓存

    公开(公告)号：KR1020010006194A

    公开(公告)日：2001-01-26

    申请号：KR1019997009274

    申请日：1998-04-07

    Applicant: 어드밴스드 마이크로 디바이시즈, 인코포레이티드

    Inventor： 만다니엘피.

    IPC: G06F11/34

    CPC classification number: G06F11/3612 ,  G06F11/261 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: 프로세서기반장치(102)는소프트웨어성능프로파일링정보를제공하기위해온칩트레이스캐시(200) 및지원회로를합체한다. 트리거제어레지스터(219a)는선택된절차에가입하는데로제1 온칩카운터를초기화및 트리거(시작)하도록구성된다.제2 트리거제어레지스터(219b)는선택된절차의절차서두가입력될시 제1 카운터를정지시키는데이용된다. 선택된절차의경과실행시간을반영하는카운터값들은온칩트레이스캐시내에저장된다. 제2 카운터가또한제공된다. 제2 카운터는연속적으로가동하지만, 그러나제2 트리거제어레지스터가야기한정지트리거사건다음에 0으로재설정된다. 정지트리거사건은또한재2 카운터의값이온칩트레이스캐시(200)내에배치되게한다. 이제2 카운터값이흥미있는절차의발생주파수를제공하는반면에, 제2 카운터는절차의실행시간에대한정보를제공한다. 목표시스템상에서실행하는후처리소프트웨어, 디버그포트를이용하는호스트시스템, 또는오프칩트레이스포획하드웨어중 하나가프로파일데이터를분석하는데이용될수 있다.

    Abstract translation: 基于处理器的设备102并入芯片上追踪缓存200和支持电路以提供软件性能分析信息。 触发控制寄存器（219A）被配置为玫瑰1芯片重置计数器和触发器（开始）加入所选择的过程中的第二触发控制寄存器（219B）是在被选定程序输入过程DUGA停止第一计数器 它被使用。 反映所选过程执行时间的计数器值存储在片上跟踪缓存中。 第二个柜台也提供。 第二个计数器连续运行，但在由第二个触发控制寄存器引起的停止触发事件之后被重置为零。 停止触发事件还导致计数器2计数器的值被置于片上跟踪高速缓存200中。 第二个计数器现在提供关于该过程的执行时间的信息，而两个计数器值以幂运算提供过程发生的频率。 在目标系统上运行的后处理软件之一，使用调试端口的主机系统或片外跟踪捕获硬件可用于分析配置文件数据。

    컴팩트한 트레이스 기록 기억장치를 포함하는 디버그 인터페이스
    264.
    发明公开
    컴팩트한 트레이스 기록 기억장치를 포함하는 디버그 인터페이스 失效
    包含紧凑跟踪记录存储的调试接口

    公开(公告)号：KR1020010006193A

    公开(公告)日：2001-01-26

    申请号：KR1019997009273

    申请日：1998-04-07

    Applicant: 어드밴스드 마이크로 디바이시즈, 인코포레이티드

    Inventor： 만다니엘피.

    IPC: G06F11/00

    CPC classification number: G06F11/3636 ,  G06F11/261 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3656 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: 내부회로에뮬레이터(ICE) 및소프트웨어디버그장치가목표프로세서를호스트시스템에인터페이스하는디버그인터페이스에의하여프로세서내에포함된다. 목표프로세서내에위치되는디버그인터페이스는, 지정된조건을검출하기위하여목표프로세서에의해생성된신호를모니터하며, 조건의표시및 조건에관련된선택정보를포함하는지정된조건의트레이스기록을생성하는트레이스컨트롤러를포함한다. 트레이스컨트롤러는트레이스정보기록을포맷하며, 이트레이스정보기록을다수의트레이스데이터저장엘리먼트내의트레이스버퍼에저장한다. 트레이스데이터저장엘리먼트는트레이스정보의타입을나타내는트레이스코드(TCODE) 필드및 트레이스정보데이터의타입을나타내는트레이스데이터(TDATA) 필드를포함하는포맷을갖는다.

    Abstract translation: 内部电路仿真器（ICE）和软件调试设备通过将目标处理器连接到主机系统的调试接口包含在处理器内。 调试接口位于一个目标处理器中，为了检测给定的条件，和监测由目标处理器产生的信号，包括用于产生指定条件包括与所述显示的选择信息跟踪记录一个跟踪控制器，和病症的条件 的。 跟踪控制器格式化跟踪信息记录并将跟踪信息记录存储在多个跟踪数据存储元件中的跟踪缓冲器中。 跟踪数据存储元件具有包括指示指示的类型的跟踪信息迹码（TCODE）字段，和类型的跟踪信息的数据的跟踪数据（TDATA）字段的格式。

    GENERATING APPROXIMATE USAGE MEASUREMENTS FOR SHARED CACHE MEMORY SYSTEMS
    265.
    发明公开
    GENERATING APPROXIMATE USAGE MEASUREMENTS FOR SHARED CACHE MEMORY SYSTEMS 审中-公开
    生成共享高速缓存存储系统的近似使用测量

    公开(公告)号：EP3224727A1

    公开(公告)日：2017-10-04

    申请号：EP15797233.2

    申请日：2015-11-09

    Applicant: Qualcomm Incorporated

    Inventor： HOWER, Derek, Robert ,  CAIN, III, Harold, Wade

    IPC: G06F12/08 ,  G06F11/34

    CPC classification number: G06F12/084 ,  G06F11/3037 ,  G06F11/3433 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2112 ,  G06F2212/282 ,  G06F2212/314 ,  Y02D10/13

    Abstract: Generating approximate usage measurements for shared cache memory systems is disclosed. In one aspect, a cache memory system is provided. The cache memory system comprises a shared cache memory system. A subset of the shared cache memory system comprises a Quality of Service identifier (QoSID) tracking tag configured to store a QoSID tracking indicator for a QoS class. The shared cache memory system further comprises a cache controller configured to receive a memory access request comprising a QoSID, and is configured to access a cache line corresponding to the memory access request. The cache controller is also configured to determine whether the QoSID of the memory access request corresponds to a cache line assigned to the QoSID. If so, the cache controller is additionally configured to update the QoSID tracking tag.

    Abstract translation: 为共享高速缓存存储器系统生成近似的使用情况测量值。 在一个方面，提供了一种高速缓冲存储器系统。 高速缓冲存储器系统包括共享高速缓冲存储器系统 共享高速缓存存储器系统的子集包括被配置为存储用于QoS类别的QoSID跟踪指示符的服务质量标识符（QoSID）跟踪标签。 共享高速缓存存储器系统还包括高速缓存控制器，该高速缓存控制器被配置为接收包括QoSID的存储器访问请求，并且被配置为访问对应于存储器访问请求的高速缓存行。 高速缓存控制器还被配置为确定存储器访问请求的QoSID是否对应于分配给QoSID的高速缓存行。 如果是，则高速缓存控制器被另外配置为更新QoSID跟踪标签。

    DATA SENDING METHOD, DATA RECEIVING METHOD AND STORAGE DEVICE
    267.
    发明公开
    DATA SENDING METHOD, DATA RECEIVING METHOD AND STORAGE DEVICE 有权
    数据发送方法，数据接收方法和存储设备

    公开(公告)号：EP2849048A1

    公开(公告)日：2015-03-18

    申请号：EP13878530.8

    申请日：2013-11-15

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： OUYANG, Ji ,  ZOU, Ye

    IPC: G06F3/06

    CPC classification number: G06F3/065 ,  G06F11/1451 ,  G06F11/1464 ,  G06F11/2094 ,  G06F11/2097 ,  G06F12/0866 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/466

    Abstract: Embodiments of the present invention provide a data sending method, a receiving method and a storage device, including receiving, by a first storage device, a first write data request sent by a host, where the first write data request carries data to be written and address information; adding a first number to the data to be written and address information, and writing the information to a cache, where the first number is a current time period number; reading the data to be written and address information corresponding to the first number from the cache; modifying the current time period number to identify information carried in a subsequent write data request; and sending the data to be written and address information to a second storage device. The present invention can increase efficiency of data replication.

    Abstract translation: 本发明实施例提供一种数据发送方法，接收方法和存储设备，包括：第一存储设备接收主机发送的第一写数据请求，所述第一写数据请求中携带待写数据; 地址信息; 向要写入的数据和地址信息添加第一编号，并将该信息写入缓存，其中第一编号为当前时间段编号; 从缓存中读取待写入的数据和与第一号码对应的地址信息; 修改当前时间段号码以识别后续写入数据请求中携带的信息; 并将要写入的数据和地址信息发送给第二存储设备。 本发明可以提高数据复制的效率。

    METHOD AND SYSTEM FOR ANALYZING THE PERFORMANCE OF MULTI-THREADED APPLICATIONS
    270.
    发明公开
    METHOD AND SYSTEM FOR ANALYZING THE PERFORMANCE OF MULTI-THREADED APPLICATIONS 审中-公开
    方法和系统性能的多线程应用情况分析

    公开(公告)号：EP2577457A2

    公开(公告)日：2013-04-10

    申请号：EP11787165.7

    申请日：2011-05-20

    Applicant: Intel Corporation

    Inventor： PEGUSHIN, Anton ,  KURYLEV, Alexandr

    IPC: G06F9/44 ,  G06F9/38

    CPC classification number: G06F11/3404 ,  G06F9/4881 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method and system to provide an analysis model to determine the specific problem(s) of a multi-threaded application. In one embodiment of the invention, the multi-thread application uses a plurality of threads for execution and each thread is assigned to a respective one of a plurality of states based on a current state of each thread. By doing so, the specific problem(s) of the multi-threaded application is determined based on the number of transitions among the plurality of states for each thread. In one embodiment of the invention, the analysis model uses worker threads transition counters or events to determine for each parallel region or algorithm of the multi-threaded application which problem has happened and how much it has affected the scalability of the parallel region or algorithm.

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